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A two-tier memory architecture for high-performance multiprocessor systems
Nguyen, T ; Srini, V ; Despain, A
International Conference on Supercomputing: Proceedings of the 2nd international conference on Supercomputing, 1988, p.326-336
ACM
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Título:
A two-tier memory architecture for high-performance multiprocessor systems
Autor:
Nguyen, T
;
Srini, V
;
Despain, A
É parte de:
International Conference on Supercomputing: Proceedings of the 2nd international conference on Supercomputing, 1988, p.326-336
Notas:
SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
Descrição:
Performance of high-speed multiprocessor systems is limited by the available bandwidth to memory and the need to synchronize write sharable data. This paper presents a new memory system that separates synchronization related data from others. The memory system has two tiers: synchronization memory and high bandwidth (HB) memory. The synchronization memory consists of snooping caches connected to a bus and is used to store synchronization variables such as locks and semaphores. The HB memory is used to store the bulk of the application program code and data. It contains caches and a high bandwidth interconnection network to memory, such as the crossbar, but does not have full snooping among caches. The two tier memory system has been evaluated by analyzing the memory behavior of the simulated parallel execution of Prolog programs. Initial results indicate that the two tier memory system potentially reduces memory interference and speeds up synchronization. Three different schemes have been studied for the caches on the HB memory and the results are presented. The two-tier memory system has potential applications in areas where synchronization is light to medium and local data is often accessed.
Editor:
ACM
Idioma:
Inglês
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