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A 0.03 mm2 delta-sigma modulator with cascaded-inverter amplifier

Wang, Zhidong ; Duan, Quanzhen ; Roh, Jeongjin

Analog integrated circuits and signal processing, 2014-11, Vol.81 (2), p.495-501 [Periódico revisado por pares]

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Título:
A 0.03 mm2 delta-sigma modulator with cascaded-inverter amplifier
Autor: Wang, Zhidong ; Duan, Quanzhen ; Roh, Jeongjin
Assuntos: Circuits and Systems ; Electrical Engineering ; Engineering ; Mixed Signal Letter ; Signal,Image and Speech Processing
É parte de: Analog integrated circuits and signal processing, 2014-11, Vol.81 (2), p.495-501
Descrição: A single stage inverter is introduced as a replacement for the conventional OTA to implement an inverter-based delta-sigma modulator. It achieves a high power and area efficiency. However, the low DC-gain and gain-bandwidth (GBW) have limited the application. This paper proposes a cascaded-inverter to increase the DC-gain and GBW, while maintaining the advantages of power and area efficiency. By cascading three inverters, the DC-gain is increased from 44 dB to 82 dB, and the GBW is increased from 100 MHz to 697 MHz. A third-order delta-sigma modulator using the proposed cascaded-inverter has been fabricated in a 0.11-μm CMOS process. When operating from a 1.2-V supply and clocked at 80 MHz, the prototype modulator achieves 59.4-dB peak SNDR over 500-kHz signal bandwidth while consuming 249 μW. Measurement results demonstrate that the application of the inverter-based amplifier, which is becoming popular due to its high power efficiency, can be extended to significantly higher speed circuits
Editor: Boston: Springer US
Idioma: Inglês

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