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In-datacenter performance analysis of a tensor processing unit

Jouppi, Norman P. ; Borchers, Al ; Boyle, Rick ; Cantin, Pierre-luc ; Chao, Clifford ; Clark, Chris ; Coriell, Jeremy ; Daley, Mike ; Dau, Matt ; Dean, Jeffrey ; Gelb, Ben ; Young, Cliff ; Ghaemmaghami, Tara Vazir ; Gottipati, Rajendra ; Gulland, William ; Hagmann, Robert ; Ho, C. Richard ; Hogberg, Doug ; Hu, John ; Hundt, Robert ; Hurt, Dan ; Ibarz, Julian ; Patil, Nishant ; Jaffey, Aaron ; Jaworski, Alek ; Kaplan, Alexander ; Khaitan, Harshit ; Killebrew, Daniel ; Koch, Andy ; Kumar, Naveen ; Lacy, Steve ; Laudon, James ; Law, James ; Patterson, David ; Le, Diemthu ; Leary, Chris ; Liu, Zhuyuan ; Lucke, Kyle ; Lundin, Alan ; MacKean, Gordon ; Maggiore, Adriana ; Mahony, Maire ; Miller, Kieran ; Nagarajan, Rahul ; Agrawal, Gaurav ; Narayanaswami, Ravi ; Ni, Ray ; Nix, Kathy ; Norrie, Thomas ; Omernick, Mark ; Penukonda, Narayana ; Phelps, Andy ; Ross, Jonathan ; Ross, Matt ; Salek, Amir ; Bajwa, Raminder ; Samadiani, Emad ; Severn, Chris ; Sizikov, Gregory ; Snelham, Matthew ; Souter, Jed ; Steinberg, Dan ; Swing, Andy ; Tan, Mercedes ; Thorson, Gregory ; Tian, Bo ; Bates, Sarah ; Toma, Horia ; Tuttle, Erick ; Vasudevan, Vijay ; Walter, Richard ; Wang, Walter ; Wilcox, Eric ; Yoon, Doe Hyun ; Bhatia, Suresh ; Boden, Nan

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.1-12

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Título:
In-datacenter performance analysis of a tensor processing unit
Autor: Jouppi, Norman P. ; Borchers, Al ; Boyle, Rick ; Cantin, Pierre-luc ; Chao, Clifford ; Clark, Chris ; Coriell, Jeremy ; Daley, Mike ; Dau, Matt ; Dean, Jeffrey ; Gelb, Ben ; Young, Cliff ; Ghaemmaghami, Tara Vazir ; Gottipati, Rajendra ; Gulland, William ; Hagmann, Robert ; Ho, C. Richard ; Hogberg, Doug ; Hu, John ; Hundt, Robert ; Hurt, Dan ; Ibarz, Julian ; Patil, Nishant ; Jaffey, Aaron ; Jaworski, Alek ; Kaplan, Alexander ; Khaitan, Harshit ; Killebrew, Daniel ; Koch, Andy ; Kumar, Naveen ; Lacy, Steve ; Laudon, James ; Law, James ; Patterson, David ; Le, Diemthu ; Leary, Chris ; Liu, Zhuyuan ; Lucke, Kyle ; Lundin, Alan ; MacKean, Gordon ; Maggiore, Adriana ; Mahony, Maire ; Miller, Kieran ; Nagarajan, Rahul ; Agrawal, Gaurav ; Narayanaswami, Ravi ; Ni, Ray ; Nix, Kathy ; Norrie, Thomas ; Omernick, Mark ; Penukonda, Narayana ; Phelps, Andy ; Ross, Jonathan ; Ross, Matt ; Salek, Amir ; Bajwa, Raminder ; Samadiani, Emad ; Severn, Chris ; Sizikov, Gregory ; Snelham, Matthew ; Souter, Jed ; Steinberg, Dan ; Swing, Andy ; Tan, Mercedes ; Thorson, Gregory ; Tian, Bo ; Bates, Sarah ; Toma, Horia ; Tuttle, Erick ; Vasudevan, Vijay ; Walter, Richard ; Wang, Walter ; Wilcox, Eric ; Yoon, Doe Hyun ; Bhatia, Suresh ; Boden, Nan
Assuntos: accelerator ; Artificial neural networks ; Central Processing Unit ; CNN ; deep learning ; DNN ; domain-specific architecture ; GPU ; Graphics processing units ; Hardware ; LSTM ; MLP ; neural network ; RNN ; Tensile stress ; TensorFlow ; TPU ; Training ; Transmission line matrix methods
É parte de: 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.1-12
Descrição: Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC - called a Tensor Processing Unit (TPU) - deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X-30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X-80X higher. Moreover, using the GPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.
Editor: ACM
Idioma: Inglês

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In-datacenter performance analysis of a tensor processing unit

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