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A Reconfigurable 74-140 Mbps LDPC Decoding System for CCSDS Standard

CHEN, Yun ; WANG, Jimin ; LI, Shixian ; XIE, Jinfou ; ZHANG, Qichen ; PARHI, Keshab K. ; ZENG, Xiaoyang

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2021, pp.2020KEP0006 [Periódico revisado por pares]

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Título:
A Reconfigurable 74-140 Mbps LDPC Decoding System for CCSDS Standard
Autor: CHEN, Yun ; WANG, Jimin ; LI, Shixian ; XIE, Jinfou ; ZHANG, Qichen ; PARHI, Keshab K. ; ZENG, Xiaoyang
Assuntos: Decoder ; Encoder ; QC-LDPC ; Reconfigurable architecture
É parte de: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2021, pp.2020KEP0006
Descrição: Accumulate Repeat-4 Jagged-Accumulate (AR4JA) codes, which are channel codes designed for deep-space communications, are a series of QC-LDPC codes. Structures of these codes' generator matrix can be exploited to design reconfigurable encoders. To make the decoder reconfigurable and achieve shorter convergence time, turbo-like decoding message passing (TDMP) is chosen as the hardware decoder's decoding schedule and normalized min-sum algorithm (NMSA) is used as decoding algorithm to reduce hardware complexity. In this paper, we propose a reconfigurable decoder and present its FPGA implementation results. The decoder can achieve throughput greater than 74 Mbps.
Editor: The Institute of Electronics, Information and Communication Engineers
Idioma: Inglês

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