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A New Design-Centering Methodology for VLSI Device Development

Aoki, Y. ; Masuda, H. ; Shimada, S. ; Sato, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 1987-05, Vol.6 (3), p.452-461 [Periódico revisado por pares]

New York, NY: IEEE

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  • Título:
    A New Design-Centering Methodology for VLSI Device Development
  • Autor: Aoki, Y. ; Masuda, H. ; Shimada, S. ; Sato, S.
  • Assuntos: Applied sciences ; Computational modeling ; Design automation ; Design methodology ; Design optimization ; Electronics ; Exact sciences and technology ; Integrated circuits ; MOSFET circuits ; Optimization methods ; Predictive models ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Supercomputers ; Threshold voltage ; Very large scale integration
  • É parte de: IEEE transactions on computer-aided design of integrated circuits and systems, 1987-05, Vol.6 (3), p.452-461
  • Notas: ObjectType-Article-2
    SourceType-Scholarly Journals-1
    ObjectType-Feature-1
    content type line 23
  • Descrição: VLSI yield optimization and design centering are two key interests in the development of submicron VLSI's. Accordingly, we have developed a new design automation technique based on simulation CAD tools. The features of this methodology are great reduction of simulation time in device optimization, and accurate prediction of process sensitivity in device performance. The approach we used was basically a modification of the "design of experiment" method. This approach makes it possible to obtain an optimum design with a large number of design parameters. The methodology was successfully applied to the optimization of a 0.5-μm MOSFET structure based on only a one-day computation by a supercomputer (S-810) using a two-dimensional device simulator. In the design centering, we assumed five objective device performances, that is, threshold voltage V/sub TH/, output conductance G/sub D/, drain current I/sub D/, V/sub TH/ dependence on gate length ΔV/sub TH/ / ΔL/sub G/, and maximum substrate current I/ sub submax/. The use of the device design centering system predicted an optimized nMOSFET with 0.52-μm gate length, 9.4-nm gate oxide thickness, and 1.6 x 10/sup 16/cm/sup-3/ substrate concentration for a given set of objective performances. Statistical variations of device characteristics were also calculated.
  • Editor: New York, NY: IEEE
  • Idioma: Inglês
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  • Realização: ABCD-USP USP   Logos de Redes Sociais: Freepik

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