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A 24-b 50-ns digital image signal processor

Nakagawa, S.-I. ; Terane, H. ; Matsumura, T. ; Segawa, H. ; Yoshimoto, M. ; Shinohara, H. ; Kato, S.-I. ; Hatanaka, M. ; Ohira, H. ; Kato, Y. ; Iwatsuki, M. ; Tabuchi, K. ; Horiba, Y.

IEEE journal of solid-state circuits, 1990-12, Vol.25 (6), p.1484-1493 [Periódico revisado por pares]

IEEE

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  • Título:
    A 24-b 50-ns digital image signal processor
  • Autor: Nakagawa, S.-I. ; Terane, H. ; Matsumura, T. ; Segawa, H. ; Yoshimoto, M. ; Shinohara, H. ; Kato, S.-I. ; Hatanaka, M. ; Ohira, H. ; Kato, Y. ; Iwatsuki, M. ; Tabuchi, K. ; Horiba, Y.
  • Assuntos: Clocks ; CMOS process ; CMOS technology ; Data processing ; Digital images ; Image processing ; Parallel architectures ; Pipelines ; Signal processing ; Very large scale integration
  • É parte de: IEEE journal of solid-state circuits, 1990-12, Vol.25 (6), p.1484-1493
  • Notas: ObjectType-Article-2
    SourceType-Scholarly Journals-1
    ObjectType-Feature-1
    content type line 23
  • Descrição: A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0- mu m CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment.< >
  • Editor: IEEE
  • Idioma: Inglês
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