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Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
Feero, B.S. ; Pande, P.P.
IEEE transactions on computers, 2009-01, Vol.58 (1), p.32-45
[Periódico revisado por pares]
New York: IEEE
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Título:
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
Autor:
Feero, B.S.
;
Pande, P.P.
Assuntos:
Artificial neural networks
;
Channels
;
Computer architecture
;
Density
;
Emerging technologies
;
Integrated circuits
;
integration and modeling
;
Interconnection architectures
;
IP (Internet Protocol)
;
Multi-core/single-chip multiprocessors
;
On-chip interconnection networks
;
Performance analysis
;
Performance Analysis and Design Aids
;
Performance evaluation
;
Semiconductors
;
System architectures
;
Three dimensional
;
Three dimensional displays
;
Throughput
;
Two dimensional
;
VLSI
É parte de:
IEEE transactions on computers, 2009-01, Vol.58 (1), p.32-45
Notas:
ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
Descrição:
The Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology for integrating a very high number of intellectual property (IP) blocks in a single die. The achievable performance benefit arising out of adopting NoCs is constrained by the performance limitation imposed by the metal wire, which is the physical realization of communication channels. With technology scaling, only depending on the material innovation will extend the lifetime of conventional interconnect systems a few technology generations. According to International Technology Roadmap for Semiconductors (ITRS) for the longer term, new interconnect paradigms are in need. The conventional two dimensional (2D) integrated circuit (IC) has limited floor-planning choices, and consequently it limits the performance enhancements arising out of NoC architectures. Three dimensional (3D) ICs are capable of achieving better performance, functionality, and packaging density compared to more traditional planar ICs. On the other hand, NoC is an enabling solution for integrating large numbers of embedded cores in a single die. 3D NoC architectures combine the benefits of these two new domains to offer an unprecedented performance gain. In this paper we evaluate the performance of 3D NoC architectures and demonstrate their superior functionality in terms of throughput, latency, energy dissipation and wiring area overhead compared to traditional 2D implementations.
Editor:
New York: IEEE
Idioma:
Inglês
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