Idioma:

FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

Shawahna, Ahmad ; Sait, Sadiq M. ; El-Maleh, Aiman

IEEE access, 2019, Vol.7, p.7823-7859 [Periódico revisado por pares]

Piscataway: IEEE

Texto completo disponível

Citações Citado por

Enviar para

Título:
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review
Autor: Shawahna, Ahmad ; Sait, Sadiq M. ; El-Maleh, Aiman
Assuntos: Acceleration ; Accelerators ; Adaptable architectures ; Application specific integrated circuits ; Artificial intelligence ; Artificial neural networks ; Central processing units ; Convolution ; convolutional neural networks (CNNs) ; CPUs ; Deep learning ; dynamic reconfiguration ; energy-efficient architecture ; Field programmable gate arrays ; field programmable gate arrays (FPGAs) ; Hardware ; hardware accelerator ; Image detection ; Integrated circuits ; Machine learning ; Neural networks ; Object recognition ; optimization ; parallel computer architecture ; reconfigurable computing ; Throughput
É parte de: IEEE access, 2019, Vol.7, p.7823-7859
Descrição: Due to recent advances in digital technologies, and availability of credible data, an area of artificial intelligence, deep learning, has emerged and has demonstrated its ability and effectiveness in solving complex learning problems not possible before. In particular, convolutional neural networks (CNNs) have demonstrated their effectiveness in the image detection and recognition applications. However, they require intensive CPU operations and memory bandwidth that make general CPUs fail to achieve the desired performance levels. Consequently, hardware accelerators that use application-specific integrated circuits, field-programmable gate arrays (FPGAs), and graphic processing units have been employed to improve the throughput of CNNs. More precisely, FPGAs have been recently adopted for accelerating the implementation of deep learning networks due to their ability to maximize parallelism and their energy efficiency. In this paper, we review the recent existing techniques for accelerating deep learning networks on FPGAs. We highlight the key features employed by the various techniques for improving the acceleration performance. In addition, we provide recommendations for enhancing the utilization of FPGAs for CNNs acceleration. The techniques investigated in this paper represent the recent trends in the FPGA-based accelerators of deep learning networks. Thus, this paper is expected to direct the future advances on efficient hardware accelerators and to be useful for deep learning researchers.
Editor: Piscataway: IEEE
Idioma: Inglês

Voltar para lista de resultados

Realização: Logos de Redes Sociais:

FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

Shawahna, Ahmad ; Sait, Sadiq M. ; El-Maleh, Aiman

Piscataway: IEEE

Buscando em bases de dados remotas. Favor aguardar.