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A chip set architecture for programmable real-time MPEG2 video encoder

Matsumura, T. ; Segawa, H. ; Matsuura, S.K.Y. ; Hanami, A. ; Yamaoka, H. ; Streitenberger, R. ; Nakagawa, S. ; Ishihara, K. ; Kasezawa, T. ; Ajioka, Y. ; Maeda, A. ; Yoshimoto, M.

Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995, p.393-396

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Título:
A chip set architecture for programmable real-time MPEG2 video encoder
Autor: Matsumura, T. ; Segawa, H. ; Matsuura, S.K.Y. ; Hanami, A. ; Yamaoka, H. ; Streitenberger, R. ; Nakagawa, S. ; Ishihara, K. ; Kasezawa, T. ; Ajioka, Y. ; Maeda, A. ; Yoshimoto, M.
Assuntos: Encoding ; Hardware ; Image reconstruction ; Laboratories ; Large scale integration ; Motion control ; Motion estimation ; Pixel ; Transform coding ; Video compression
É parte de: Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995, p.393-396
Descrição: This paper describes a chip set architecture for a programmable video encoder based on the MPEG2 main profile at main level (MP@ML). The chip set consists of a Controller-LSI (C-LSI), a macroblock level Pixel Processor-LSI (P-LSI) and a Motion Estimation-LSI (ME-LSI). The chip set combined with synchronous DRAMs (SDRAM) supports the whole layer processing including rate-control and realizes the real-time encoding for ITU-R-601 resolution video (720/spl times/480 pixels at 30 frame/s) with glueless logic. The exhaustive motion estimation capability is scalable up to +-63.5/+-15.5 in the horizontal/vertical directions. This chip set solution can realize a low cost MPEG2 video encoder system with excellent video quality on a small PC card.
Editor: IEEE
Idioma: Inglês

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