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On-Chip Interconnection Architecture of the Tile Processor

Wentzlaff, D. ; Griffin, P. ; Hoffmann, H. ; Liewei Bao ; Edwards, B. ; Ramey, C. ; Mattina, M. ; Chyi-Chang Miao ; Brown, J.F. ; Agarwal, A.

IEEE MICRO, 2007-09, Vol.27 (5), p.15-31 [Periódico revisado por pares]

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Título:
On-Chip Interconnection Architecture of the Tile Processor
Autor: Wentzlaff, D. ; Griffin, P. ; Hoffmann, H. ; Liewei Bao ; Edwards, B. ; Ramey, C. ; Mattina, M. ; Chyi-Chang Miao ; Brown, J.F. ; Agarwal, A.
Assuntos: Architecture ; Bandwidth ; Communication networks ; Computer architecture ; Hardware ; Interconnect ; Interconnection ; Libraries ; Mesh networks ; Microprocessors ; MIMD processors ; multicore architectures ; Multicore processing ; Multiprocessor interconnection networks ; Network topologies ; Network-on-a-chip ; Networks ; on-chip interconnection networks ; parallel architectures ; Two dimensional
É parte de: IEEE MICRO, 2007-09, Vol.27 (5), p.15-31
Notas: ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
Descrição: IMesh, the tile processor architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. taking advantage of the five networks, the C-based ILIB interconnection library efficiently maps program communication across the on-chip interconnect. the tile processor's first implementation, the tile64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 Ghz.
Editor: Los Alamitos: IEEE
Idioma: Inglês

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