Idioma:

45nm High-k + metal gate strain-enhanced transistors

Auth, C. ; Cappellani, A. ; Chun, J.-S. ; Dalis, A. ; Davis, A. ; Ghani, T. ; Glass, G. ; Glassman, T. ; Harper, M. ; Hattendorf, M. ; Hentges, P. ; Jaloviar, S. ; Joshi, S. ; Klaus, J. ; Kuhn, K. ; Lavric, D. ; Lu, M. ; Mariappan, H. ; Mistry, K. ; Norris, B. ; Rahhal-orabi, N. ; Ranade, P. ; Sandford, J. ; Shifren, L. ; Souw, V. ; Tone, K. ; Tambwe, F. ; Thompson, A. ; Towner, D. ; Troeger, T. ; Vandervoorn, P. ; Wallace, C. ; Wiedemer, J. ; Wiegand, C.

2008 Symposium on VLSI Technology, 2008, p.128-129

Texto completo disponível

Citações Citado por

Título:
45nm High-k + metal gate strain-enhanced transistors
Autor: Auth, C. ; Cappellani, A. ; Chun, J.-S. ; Dalis, A. ; Davis, A. ; Ghani, T. ; Glass, G. ; Glassman, T. ; Harper, M. ; Hattendorf, M. ; Hentges, P. ; Jaloviar, S. ; Joshi, S. ; Klaus, J. ; Kuhn, K. ; Lavric, D. ; Lu, M. ; Mariappan, H. ; Mistry, K. ; Norris, B. ; Rahhal-orabi, N. ; Ranade, P. ; Sandford, J. ; Shifren, L. ; Souw, V. ; Tone, K. ; Tambwe, F. ; Thompson, A. ; Towner, D. ; Troeger, T. ; Vandervoorn, P. ; Wallace, C. ; Wiedemer, J. ; Wiegand, C.
Assuntos: International Electron Devices Meeting ; Logic gates ; Materials ; Metals ; MOS devices ; Stress ; Transistors
É parte de: 2008 Symposium on VLSI Technology, 2008, p.128-129
Descrição: Two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-k transistors. The second feature is the extension of 193 nm dry lithography to the 45 nm technology node pitches. Use of these features has enabled industry-leading transistor performance and the first high volume 45 nm high-k + metal gate technology.
Editor: IEEE
Idioma: Inglês

Voltar para lista de resultados