FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

Arul Murugan, C. ; Karthigaikumar, P. ; Sathya Priya, Sridevi

Automatika, 2020-10, Vol.61 (4), p.682-693 [Periódico revisado por pares]

Ljubljana: Taylor & Francis

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