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Pipelining a triggered processing element

Repetti, Thomas ; Cerqueira, João ; Kim, Martha ; Seok, Mingoo

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, p.96-108

ACM

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  • Título:
    Pipelining a triggered processing element
  • Autor: Repetti, Thomas ; Cerqueira, João ; Kim, Martha ; Seok, Mingoo
  • Assuntos: Computer architecture ; Delays ; design-space exploration ; Field programmable gate arrays ; Hazards ; low-power design ; Microarchitecture ; pipeline hazards ; Pipeline processing ; Registers ; Spatial architectures
  • É parte de: 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, p.96-108
  • Descrição: Programmable spatial architectures composed of ensembles of autonomous fixed-ISA processing elements offer a compelling design point between the flexibility of an FPGA and the compute density of a GPU or shared-memory many-core. The design regularity of spatial architectures demands examination of the processing element microarchitecture early in the design process to optimize overall efficiency. This paper considers the microarchitectural issues surrounding pipelining a spatial processing element with triggered-instruction control. We propose two new techniques to mitigate pipeline hazards particular to spatial accelerators and non-program-counter architectures, evaluating them using in-vivo performance counters from an FPGA prototype coupled with a rigorous VLSI power and timing estimation methodology. We consider the effect of modern, post-Dennard-scaling CMOS technology on the energy-delay tradeoffs and identify a set of microarchitectures optimal for both high-performance and low-power application settings. Our analysis reveals the effectiveness of our hazard mitigation techniques as well as the range of microarchitectures designers might consider when selecting a processing element for triggered spatial accelerators.
  • Editor: ACM
  • Idioma: Inglês
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  • Realização: ABCD-USP USP   Logos de Redes Sociais: Freepik

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