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ChipCflow: tool for convert C code in a static dataflow architecture in reconfigurable hardware

Silva, Antonio Carlos Fernandes Da

Biblioteca Digital de Teses e Dissertações da USP; Universidade de São Paulo; Instituto de Ciências Matemáticas e de Computação 2015-02-19

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  • Título:
    ChipCflow: tool for convert C code in a static dataflow architecture in reconfigurable hardware
  • Autor: Silva, Antonio Carlos Fernandes Da
  • Orientador: Silva, Jorge Luiz e
  • Assuntos: Vhdl; Chipcflow; Código C; Compilador; Fpga; Fluxo De Dados; Vhdl; Dataflow; Compiler; C Code
  • Notas: Tese (Doutorado)
  • Descrição: A growing search for alternative architectures and softwares have been noted in the last years. This search happens due to the advance of hardware technology and such advances must be complemented by innovations on design methodologies, test and verification techniques in order to use technology effectively. Alternative architectures and softwares, in general, explores the parallelism of applications, differently to Von Neumann model. Among high performance alternative architectures, there is the Dataflow Architecture. In this kind of architecture, the process of program execution is determined by data availability, thus the parallelism is intrinsic in these systems. The dataflow architectures become again a highlighted search area due to hardware advances, in particular, the advances of Reconfigurable Computing and Field Programmable Gate Arrays (FPGAs). ChipCflow projet is a tool for execution of algorithms using dynamic dataflow graph in FPGA. In this thesis, the development of a code conversion tool to generate aplications in a static dataflow architecture, is described. Also the ChipCflow project where the code conversion tool is part, is presented. The specification of algorithm to be converted is made in C language and converted to a hadware description language, respecting the proposed by ChipCflow project. The results are the proof of concept of converting a high-level language code for dataflow architecture to be used into a FPGA.
  • DOI: 10.11606/T.55.2015.tde-30062015-141638
  • Editor: Biblioteca Digital de Teses e Dissertações da USP; Universidade de São Paulo; Instituto de Ciências Matemáticas e de Computação
  • Data de criação/publicação: 2015-02-19
  • Formato: Adobe PDF
  • Idioma: Inglês
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  • Realização: ABCD-USP USP   Logos de Redes Sociais: Freepik

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