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Counter Tree: A Scalable Counter Architecture for Per-Flow Traffic Measurement

Chen, Min ; Chen, Shigang ; Cai, Zhiping

IEEE/ACM transactions on networking, 2017-04, Vol.25 (2), p.1249-1262 [Periódico revisado por pares]

New York: IEEE

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  • Título:
    Counter Tree: A Scalable Counter Architecture for Per-Flow Traffic Measurement
  • Autor: Chen, Min ; Chen, Shigang ; Cai, Zhiping
  • Assuntos: Anomalies ; Computer architecture ; counter architecture ; counter sharing ; Counting ; Estimation ; flow size ; Memory management ; Performance enhancement ; Radiation detectors ; Random access memory ; Routers ; Routing ; Size measurement ; Static random access memory ; Switches ; Switching theory ; Traffic control ; Traffic engineering ; Traffic flow ; Traffic measurement ; virtual counter
  • É parte de: IEEE/ACM transactions on networking, 2017-04, Vol.25 (2), p.1249-1262
  • Descrição: Per-flow traffic measurement, which is to count the number of packets for each active flow during a certain measurement period, has many applications in traffic engineering, classification of routing distribution or network usage pattern, service provision, anomaly detection, and network forensics. In order to keep up with the high throughput of modern routers or switches, the online module for per-flow traffic measurement should use high-bandwidth SRAM that allows fast memory accesses. Due to limited SRAM space, exact counting, which requires to keep a counter for each flow, does not scale to large networks consisting of numerous flows. Some recent work takes a different approach to estimate the flow sizes using counter architectures that can fit into tight SRAM. However, existing counter architectures have limitations, either still requiring considerable SRAM space or having a small estimation range. In this paper, we design a scalable counter architecture called Counter Tree, which leverages a 2-D counter sharing scheme to achieve far better memory efficiency and in the meantime extend estimation range significantly. Furthermore, we improve the performance of Counter Tree by adding a status bit to each counter. Extensive experiments with real network traces demonstrate that our counter architecture can produce accurate estimates for flows of all sizes under very tight memory space.
  • Editor: New York: IEEE
  • Idioma: Inglês
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  • Realização: ABCD-USP USP   Logos de Redes Sociais: Freepik

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