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An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces

Malekzadeh-Arasteh, Omid ; Pu, Haoran ; Lim, Jeffrey ; Liu, Charles Yu ; Do, An H. ; Nenadic, Zoran ; Heydari, Payam

IEEE transactions on biomedical circuits and systems, 2020-04, Vol.14 (2), p.332-342 [Periódico revisado por pares]

United States: IEEE

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Título:
An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces
Autor: Malekzadeh-Arasteh, Omid ; Pu, Haoran ; Lim, Jeffrey ; Liu, Charles Yu ; Do, An H. ; Nenadic, Zoran ; Heydari, Payam
Assuntos: Amplifiers, Electronic ; Analog signal processing ; Architecture ; Arrays ; Bandwidth ; Brain ; Brain - diagnostic imaging ; Brain - physiology ; Brain architecture ; brain signal acquisition ; Brain-Computer Interfaces ; brain-machine interfaces ; CMOS ; Computer architecture ; Digitization ; EEG ; electrocorticography (ECoG) ; Electrocorticography - instrumentation ; Electroencephalography ; Energy efficiency ; Equipment Design ; Feature extraction ; high-density array ; Humans ; Impedance ; Interfaces ; Man-machine interfaces ; Multiplexing ; Noise levels ; Power demand ; Power efficiency ; Power management ; Signal processing ; Signal Processing, Computer-Assisted - instrumentation ; ultra-low power
É parte de: IEEE transactions on biomedical circuits and systems, 2020-04, Vol.14 (2), p.332-342
Notas: ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
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Descrição: This article presents an energy-efficient electrocorticography (ECoG) array architecture for fully-implantable brain machine interface systems. A novel dual-mode analog signal processing method is introduced that extracts neural features from high-\gamma band (80-160 Hz) at the early stages of signal acquisition. Initially, brain activity across the full-spectrum is momentarily observed to compute the feature weights in the digital back-end during full-band mode operation. Subsequently, these weights are fed back to the front-end and the system reverts to base-band mode to perform feature extraction. This approach utilizes a distinct optimized signal pathway based on power envelope extraction, resulting in 1.72× power reduction in the analog blocks and up to 50× potential power savings for digitization and processing (implemented off-chip in this article). A prototype incorporating a 32-channel ultra-low power signal acquisition front-end is fabricated in 180 nm CMOS process with 0.8 V supply. This chip consumes 1.05 \muW (0.205 \muW for feature extraction only) power and occupies 0.245 {\text{mm}}^{\text{2}} die area per channel. The chip measurement shows better than 76.5-dB common-mode rejection ratio (CMRR), 4.09 noise efficiency factor (NEF), and 10.04 power efficiency factor (PEF). In-vivo human tests have been carried out with electroencephalography and ECoG signals to validate the performance and dual-mode operation in comparison to commercial acquisition systems.
Editor: United States: IEEE
Idioma: Inglês

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An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces

Malekzadeh-Arasteh, Omid ; Pu, Haoran ; Lim, Jeffrey ; Liu, Charles Yu ; Do, An H. ; Nenadic, Zoran ; Heydari, Payam

United States: IEEE

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