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Refined by: creation date: 1973To1988 remove subject: Computer Architecture remove Journal Title: Ieee Transactions On Computers remove
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Topological properties of hypercubes
Topological properties of hypercubes
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Topological properties of hypercubes

Saad, Y. ; Schultz, M.H.

IEEE Trans. Comput.; (United States), 1988-07, Vol.37 (7), p.867-872 [Peer Reviewed Journal]

New York, NY: IEEE

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2
The NYU Ultracomputer-Designing an MIMD Shared Memory Parallel Computer
The NYU Ultracomputer-Designing an MIMD Shared Memory Parallel Computer
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The NYU Ultracomputer-Designing an MIMD Shared Memory Parallel Computer

Gottlieb, A ; Grishman, R ; McAuliffe, K P ; Snir, M ; Kruskal, C P ; Rudolph, L

IEEE Trans. Comput.; (United States), 1983-02, Vol.C-32 (2), p.175-189 [Peer Reviewed Journal]

United States: IEEE

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3
A VLIW architecture for a trace scheduling compiler
A VLIW architecture for a trace scheduling compiler
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A VLIW architecture for a trace scheduling compiler

Colwell, R.P. ; Nix, R.P. ; O'Donnell, J.J. ; Papworth, D.B. ; Rodman, P.K.

IEEE Trans. Comput.; (United States), 1988-08, Vol.37 (8), p.967-979 [Peer Reviewed Journal]

New York, NY: IEEE

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4
Approximate analysis of fork/join synchronization in parallel queues
Approximate analysis of fork/join synchronization in parallel queues
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Approximate analysis of fork/join synchronization in parallel queues

Nelson, R. ; Tantawi, A.N.

IEEE Trans. Comput.; (United States), 1988-06, Vol.37 (6), p.739-743 [Peer Reviewed Journal]

New York, NY: IEEE

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5
On a Class of Multistage Interconnection Networks
On a Class of Multistage Interconnection Networks
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On a Class of Multistage Interconnection Networks

Wu, C-L ; Feng, T-Y

IEEE transactions on computers, 1980-08, Vol.C-29 (8), p.694-702 [Peer Reviewed Journal]

IEEE

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6
Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures
Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures
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Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures

Rashid, R. ; Tevanian, A. ; Young, M. ; Golub, D. ; Baron, R. ; Black, D. ; Bolosky, W.J. ; Chew, J.

IEEE Trans. Comput.; (United States), 1988-08, Vol.37 (8), p.896-908 [Peer Reviewed Journal]

New York, NY: IEEE

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7
Hypernet: A Communication-Efficient Architecture for Constructing Massively Parallel Computers
Hypernet: A Communication-Efficient Architecture for Constructing Massively Parallel Computers
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Hypernet: A Communication-Efficient Architecture for Constructing Massively Parallel Computers

Hwang, Kai ; Ghosh, Joydeep

IEEE Trans. Comput.; (United States), 1987-12, Vol.C-36 (12), p.1450-1466 [Peer Reviewed Journal]

New York, NY: IEEE

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8
Processor Control Flow Monitoring Using Signatured Instruction Streams
Processor Control Flow Monitoring Using Signatured Instruction Streams
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Processor Control Flow Monitoring Using Signatured Instruction Streams

SCHUETTE, M. A ; SHEN, J. P

IEEE Trans. Comput.; (United States), 1987-03, Vol.C-36 (3), p.264-276 [Peer Reviewed Journal]

New York, NY: IEEE

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9
VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
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VLSI Architectures for Computing Multiplications and Inverses in GF(2m)

Wang, C. C. ; Truong, T. K. ; Shao, H. M. ; Deutsch, L. J. ; Omura, J. K.

IEEE transactions on computers, 1985-08, Vol.C-34 (8), p.709-717 [Peer Reviewed Journal]

Legacy CDMS: IEEE

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10
Partitioning problems in parallel, pipelined, and distributed computing
Partitioning problems in parallel, pipelined, and distributed computing
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Partitioning problems in parallel, pipelined, and distributed computing

Bokhari, Shahid H.

IEEE Trans. Comput.; (United States), 1988-01, Vol.37 (1), p.48-57 [Peer Reviewed Journal]

Legacy CDMS: Institute of Electrical and Electronics Engineers

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