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Dedicated Instruction Set for Pattern-based Data Transfers: an Experimental Validation on Systems Containing In-Memory Computing Units
Dedicated Instruction Set for Pattern-based Data Transfers: an Experimental Validation on Systems Containing In-Memory Computing Units
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Dedicated Instruction Set for Pattern-based Data Transfers: an Experimental Validation on Systems Containing In-Memory Computing Units

Mambu, Kevin ; Charles, Henri-Pierre ; Kooli, Maha

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1 [Periódico revisado por pares]

New York: IEEE

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Back to Homogeneous Computing: A Tightly-Coupled Neuromorphic Processor With Neuromorphic ISA
Back to Homogeneous Computing: A Tightly-Coupled Neuromorphic Processor With Neuromorphic ISA
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Back to Homogeneous Computing: A Tightly-Coupled Neuromorphic Processor With Neuromorphic ISA

Yang, Zhijie ; Wang, Lei ; Shi, Wei ; Wang, Yao ; Tie, Junbo ; Wang, Feng ; Yu, Xiang ; Peng, Linghui ; Xiao, Chao ; Xiao, Xun ; Yao, Yao ; Zhou, Gan ; Yu, Xuhu ; Gong, Rui ; Zhao, Xia ; Tang, Yuhua ; Xu, Weixia

IEEE transactions on parallel and distributed systems, 2023-11, Vol.34 (11), p.1-18 [Periódico revisado por pares]

IEEE

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Exact and approximate algorithms for the extension of embedded processor instruction sets
Exact and approximate algorithms for the extension of embedded processor instruction sets
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Exact and approximate algorithms for the extension of embedded processor instruction sets

Pozzi, L. ; Atasu, K. ; Ienne, P.

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-07, Vol.25 (7), p.1209-1229 [Periódico revisado por pares]

New York: IEEE

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4
Enhancing a Near-Term Quantum Accelerator's Instruction Set Architecture for Materials Science Applications
Enhancing a Near-Term Quantum Accelerator's Instruction Set Architecture for Materials Science Applications
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Enhancing a Near-Term Quantum Accelerator's Instruction Set Architecture for Materials Science Applications

Zou, Xiang ; Premaratne, Shavindra P. ; Rol, M. Adriaan ; Johri, Sonika ; Ostroukh, Viacheslav ; Michalak, David J. ; Caudillo, Roman ; Clarke, James S. ; DiCarlo, Leonardo ; Matsuura, A. Y.

IEEE transactions on quantum engineering, 2020, Vol.1, p.1-7 [Periódico revisado por pares]

IEEE

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5
Designing RISC-V Instruction Set Extensions for Artificial Neural Networks: An LLVM Compiler-Driven Perspective
Designing RISC-V Instruction Set Extensions for Artificial Neural Networks: An LLVM Compiler-Driven Perspective
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Designing RISC-V Instruction Set Extensions for Artificial Neural Networks: An LLVM Compiler-Driven Perspective

Balasubramanian, Karthikeyan Kalyanasundaram ; Salvo, Mirco Di ; Rocchia, Walter ; Decherchi, Sergio ; Crepaldi, Marco

IEEE access, 2024, Vol.12, p.55925-55944 [Periódico revisado por pares]

IEEE

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6
P4 and NetFPGA-Based Secure In-Network Computing Architecture for AI-Enabled Industrial Internet of Things
P4 and NetFPGA-Based Secure In-Network Computing Architecture for AI-Enabled Industrial Internet of Things
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P4 and NetFPGA-Based Secure In-Network Computing Architecture for AI-Enabled Industrial Internet of Things

Sankaran, Ganesh C. ; Sivalingam, Krishna M. ; Gondaliya, Harsh

IEEE internet of things journal, 2023-02, Vol.10 (4), p.2979-2994

Piscataway: IEEE

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7
Ensuring Consistency between Cycle-Accurate and Instruction Set Simulators
Ensuring Consistency between Cycle-Accurate and Instruction Set Simulators
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Ensuring Consistency between Cycle-Accurate and Instruction Set Simulators

Jebali, Fatma ; Potop-Butucaru, Dumitru

2018 18th International Conference on Application of Concurrency to System Design (ACSD), 2018, p.105-114

IEEE

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A Survey of Parallel Programming Models and Tools in the Multi and Many-Core Era
A Survey of Parallel Programming Models and Tools in the Multi and Many-Core Era
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A Survey of Parallel Programming Models and Tools in the Multi and Many-Core Era

Diaz, J. ; Munoz-Caro, C. ; Nino, A.

IEEE transactions on parallel and distributed systems, 2012-08, Vol.23 (8), p.1369-1386 [Periódico revisado por pares]

IEEE

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9
The Microarchitecture of DOJO, Tesla's Exa-Scale Computer
The Microarchitecture of DOJO, Tesla's Exa-Scale Computer
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The Microarchitecture of DOJO, Tesla's Exa-Scale Computer

Talpes, Emil ; Sarma, Debjit Das ; Williams, Doug ; Arora, Sahil ; Kunjan, Thomas ; Floering, Benjamin ; Jalote, Ankit ; Hsiong, Christopher ; Poorna, Chandrasekhar ; Samant, Vaidehi ; Sicilia, John ; Nivarti, Anantha Kumar ; Ramachandran, Raghuvir ; Fischer, Tim ; Herzberg, Ben ; McGee, Bill ; Venkataramanan, Ganesh ; Banon, Pete

IEEE MICRO, 2023-05, Vol.43 (3), p.1-5 [Periódico revisado por pares]

IEEE

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10
HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols
HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols
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HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols

Oswald, Nicolai ; Nagarajan, Vijay ; Sorin, Daniel J. ; Gavrielatos, Vasilis ; Olausson, Theo X. ; Carr, Reece

IEEE MICRO, 2023-07, Vol.43 (4), p.1-8 [Periódico revisado por pares]

Los Alamitos: IEEE

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