skip to main content
Idioma:
Resultados 1 2 3 4 5 next page
Refinado por: Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover
Result Number Material Type Add to My Shelf Action Record Details and Options
1
Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints
Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints
Material Type:
Artigo 		Adicionar ao Meu Espaço

Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints

Chabini, N. ; Wolf, W.

IEEE transactions on very large scale integration (VLSI) systems, 2005-10, Vol.13 (10), p.1113-1126 [Periódico revisado por pares]

Piscataway, NJ: IEEE

Texto completo disponível

Citações Citado por
2
Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity
Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity
Material Type:
Artigo 		Adicionar ao Meu Espaço

Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity

Vezyrtzis, Christos ; Tsividis, Yannis ; Nowick, Steven M.

IEEE transactions on very large scale integration (VLSI) systems, 2015-10, Vol.23 (10), p.2009-2022 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por
3
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling
Material Type:
Artigo 		Adicionar ao Meu Espaço

Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

Chabini, N. ; Wolf, W.

IEEE transactions on very large scale integration (VLSI) systems, 2004-06, Vol.12 (6), p.573-589 [Periódico revisado por pares]

Piscataway, NJ: IEEE

Texto completo disponível

Citações Citado por
4
Four-Level Forms for Memristive Material Implication Logic
Four-Level Forms for Memristive Material Implication Logic
Material Type:
Artigo 		Adicionar ao Meu Espaço

Four-Level Forms for Memristive Material Implication Logic

Marranghello, Felipe S. ; Callegaro, Vinicius ; Reis, Andre I. ; Ribas, Renato P.

IEEE transactions on very large scale integration (VLSI) systems, 2019-05, Vol.27 (5), p.1228-1232 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por
5
Asynchronous Data-Driven Circuit Synthesis
Asynchronous Data-Driven Circuit Synthesis
Material Type:
Artigo 		Adicionar ao Meu Espaço

Asynchronous Data-Driven Circuit Synthesis

Taylor, Sam ; Edwards, Doug A ; Plana, Luis A ; Tarazona D, Luis A

IEEE transactions on very large scale integration (VLSI) systems, 2010-07, Vol.18 (7), p.1093-1106 [Periódico revisado por pares]

New York, NY: IEEE

Texto completo disponível

Citações Citado por
6
Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication
Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication
Material Type:
Artigo 		Adicionar ao Meu Espaço

Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication

McLaughlin, W.F. ; Mitra, A. ; Nowick, S.M.

IEEE transactions on very large scale integration (VLSI) systems, 2009-07, Vol.17 (7), p.923-928 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por
7
On the Design of RNS Reverse Converters for the Four-Moduli Set {2n + 1, 2n ― 1, 2n, 2n+1 + 1}
On the Design of RNS Reverse Converters for the Four-Moduli Set {2n + 1, 2n ― 1, 2n, 2n+1 + 1}
Material Type:
Artigo 		Adicionar ao Meu Espaço

On the Design of RNS Reverse Converters for the Four-Moduli Set {2n + 1, 2n ― 1, 2n, 2n+1 + 1}

SOUSA, Leonel ; ANTAO, Samuel ; CHAVES, Ricardo

IEEE transactions on very large scale integration (VLSI) systems, 2013-10, Vol.21 (10), p.1945-1949 [Periódico revisado por pares]

New York, NY: Institute of Electrical and Electronics Engineers

Texto completo disponível

Citações Citado por
8
An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks
An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks
Material Type:
Artigo 		Adicionar ao Meu Espaço

An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks

Islam, Md Najrul ; Shrestha, Rahul ; Chowdhury, Shubhajit Roy

IEEE transactions on very large scale integration (VLSI) systems, 2022-12, Vol.30 (12), p.1-11 [Periódico revisado por pares]

IEEE

Texto completo disponível

Citações Citado por
9
Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging
Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging
Material Type:
Artigo 		Adicionar ao Meu Espaço

Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging

Guido, James S. ; Yakovlev, Alexandre

IEEE transactions on very large scale integration (VLSI) systems, 2015-02, Vol.23 (2), p.292-305 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por
10
An Ultra Low Power Baseband Transceiver IC for Wireless Body Area Network in 0.18- \mu m CMOS Technology
An Ultra Low Power Baseband Transceiver IC for Wireless Body Area Network in 0.18- \mu m CMOS Technology
Material Type:
Artigo 		Adicionar ao Meu Espaço

An Ultra Low Power Baseband Transceiver IC for Wireless Body Area Network in 0.18- \mu m CMOS Technology

Liu, Xin ; Zheng, Yuanjin ; Zhao, Bin ; Wang, Yisheng ; Phyu, Myint Wai

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1418-1428 [Periódico revisado por pares]

New York, NY: IEEE

Texto completo disponível

Citações Citado por
Resultados 1 2 3 4 5 next page

Personalize Seus Resultados

  1. Editar

Refine Search Results

Expandir Meus Resultados

  1.   

Data de Publicação 

De até
Refinar
  1. Antes de1998  (30)
  2. 1998Até2003  (129)
  3. 2004Até2009  (285)
  4. 2010Até2016  (285)
  5. Após 2016  (38)
  6. Mais opções open sub menu

  • Realização: ABCD-USP USP   Logos de Redes Sociais: Freepik

Buscando em bases de dados remotas. Favor aguardar.