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1
The Architecture of digital computers
The Architecture of digital computers
Material Type:
Book 		Add to e-Shelf

The Architecture of digital computers

R. G. Garside

Oxford Clarendon Press New York Oxford University Press 1980

Available at EEL - Engenharia de Materiais    (004.2 G243a ) and other locations(GetIt)

2
Evaluating supercomputers strategies for exploiting, evaluating, and benchmarking computers with advanced architectures
Evaluating supercomputers strategies for exploiting, evaluating, and benchmarking computers with advanced architectures
Material Type:
Book 		Add to e-Shelf

Evaluating supercomputers strategies for exploiting, evaluating, and benchmarking computers with advanced architectures

Aad J. van der Steen

London New York Chapman & Hall 1990

Available at EPBC - Esc. Politécnica-Bib Central    (004.382.2 St32e )(GetIt)

3
Investigação de técnicas fotônicas de chaveamento aplicadas em arquiteturas paralelas.
Investigação de técnicas fotônicas de chaveamento aplicadas em arquiteturas paralelas.
Material Type:
Ph.D. Dissertation 		Add to e-Shelf

Investigação de técnicas fotônicas de chaveamento aplicadas em arquiteturas paralelas.

Martins, João Eduardo Machado Perea

Biblioteca Digital de Teses e Dissertações da USP; Universidade de São Paulo; Instituto de Física de São Carlos 1998-03-20

Online access. The library also has physical copies.

4
Arquitetura multi-core reconfigurável para detecção de pedestres baseada em visão
Arquitetura multi-core reconfigurável para detecção de pedestres baseada em visão
Material Type:
Ph.D. Dissertation 		Add to e-Shelf

Arquitetura multi-core reconfigurável para detecção de pedestres baseada em visão

Holanda, Jose Arnaldo Mascagni De

Biblioteca Digital de Teses e Dissertações da USP; Universidade de São Paulo; Instituto de Ciências Matemáticas e de Computação 2017-05-17

Online access. The library also has physical copies.

5
The architecture of microprocessors
The architecture of microprocessors
Material Type:
Book 		Add to e-Shelf

The architecture of microprocessors

F. Anceau Wilson, Manissa J. Dobrée; Milligan, Derek

Wokingham, England Reading, Mass. Addison-Wesley c1986

Available at FAU - Fac. Arquitetura e Urbanismo    (621.38195 An21a ) and other locations(GetIt)

6
Exploration of FPGA-based hardware designs for QR decomposition for solving stiff ODE numerical methods using the HARP hybrid architecture
Exploration of FPGA-based hardware designs for QR decomposition for solving stiff ODE numerical methods using the HARP hybrid architecture
Material Type:
Article 		Add to e-Shelf

Exploration of FPGA-based hardware designs for QR decomposition for solving stiff ODE numerical methods using the HARP hybrid architecture

Carlos Alberto Oliveira de Souza Junior João Bispo; João Manuel Paiva Cardoso; Pedro C Diniz; Eduardo Marques

Electronics Basel : MDPI v. 9, n. 5, p. 1-14, 2020

Basel 2020

Available at ICMC - Inst. Ciên. Mat. Computação    (PROD-2997706 )(GetIt)

7
Computation structures
Computation structures
Material Type:
Book 		Add to e-Shelf

Computation structures

Stephen A. Ward Robert H Halstead

Cambridge, Mass. MIT Press New York McGraw-Hill c1990

Available at EPBC - Esc. Politécnica-Bib Central    (004.2 W217c ) and other locations(GetIt)

8
DaDianNao: A Machine-Learning Supercomputer
DaDianNao: A Machine-Learning Supercomputer
Material Type:
Conference Proceeding 		Add to e-Shelf

DaDianNao: A Machine-Learning Supercomputer

Chen, Yunji ; Luo, Tao ; Liu, Shaoli ; Zhang, Shijin ; He, Liqiang ; Wang, Jia ; Li, Ling ; Chen, Tianshi ; Xu, Zhiwei ; Sun, Ninghui ; Temam, Olivier

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, p.609-622

IEEE Computer Society

Full text available

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9
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
Material Type:
Article 		Add to e-Shelf

Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

Ma, Yufei ; Cao, Yu ; Vrudhula, Sarma ; Seo, Jae-sun

IEEE transactions on very large scale integration (VLSI) systems, 2018-07, Vol.26 (7), p.1354-1367 [Peer Reviewed Journal]

New York: IEEE

Full text available

Citations Cited by
10
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
Material Type:
Article 		Add to e-Shelf

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Ueno, Rei ; Homma, Naofumi ; Morioka, Sumio ; Miura, Noriyuki ; Matsuda, Kohei ; Nagata, Makoto ; Bhasin, Shivam ; Mathieu, Yves ; Graba, Tarik ; Danger, Jean-Luc

IEEE transactions on computers, 2020-04, Vol.69 (4), p.534-548 [Peer Reviewed Journal]

IEEE

Full text available

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