Result Number | Material Type | Add to My Shelf Action | Record Details and Options |
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Material Type: Artigo
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Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal ProcessingZhu, Ning ; Goh, Wang Ling ; Zhang, Weija ; Yeo, Kiat Seng ; Kong, Zhi HuiIEEE transactions on very large scale integration (VLSI) systems, 2010-08, Vol.18 (8), p.1225-1229 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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2 |
Material Type: Artigo
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Low-Power and Area-Efficient Carry Select AdderRamkumar, B. ; Kittur, H. M.IEEE transactions on very large scale integration (VLSI) systems, 2012-02, Vol.20 (2), p.371-375 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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3 |
Material Type: Artigo
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The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and AnalysisWenping Wang ; Shengqi Yang ; Bhardwaj, S. ; Vrudhula, S. ; Liu, F. ; Yu CaoIEEE transactions on very large scale integration (VLSI) systems, 2010-02, Vol.18 (2), p.173-183 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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4 |
Material Type: Artigo
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Design of Testable Reversible Sequential CircuitsThapliyal, H. ; Ranganathan, N. ; Kotiyal, S.IEEE transactions on very large scale integration (VLSI) systems, 2013-07, Vol.21 (7), p.1201-1209 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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5 |
Material Type: Artigo
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A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuitsMoaiyeri, Mohammad Hossein ; Mirzaee, Reza Faghih ; Doostaregan, Akbar ; Navi, Keivan ; Hashemipour, OmidIET computers & digital techniques, 2013-07, Vol.7 (4), p.167-181 [Periódico revisado por pares]Stevenage: The Institution of Engineering and TechnologyTexto completo disponível |
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6 |
Material Type: Artigo
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Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic StyleGoel, S. ; Kumar, A. ; Bayoumi, M.A.IEEE transactions on very large scale integration (VLSI) systems, 2006-12, Vol.14 (12), p.1309-1321 [Periódico revisado por pares]Piscataway, NJ: IEEETexto completo disponível |
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7 |
Material Type: Artigo
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Scalable Packet Classification on FPGAWeirong Jiang ; Prasanna, V. K.IEEE transactions on very large scale integration (VLSI) systems, 2012-09, Vol.20 (9), p.1668-1680 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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8 |
Material Type: Artigo
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Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETsKarmakar, Supriya ; Chandy, John A. ; Jain, Faquir C.IEEE transactions on very large scale integration (VLSI) systems, 2013-05, Vol.21 (5), p.793-806 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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9 |
Material Type: Artigo
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Understanding the Effect of Process Variations on the Delay of Static and Domino LogicAlioto, Massimo ; Palumbo, Gaetano ; Pennisi, MelitaIEEE transactions on very large scale integration (VLSI) systems, 2010-05, Vol.18 (5), p.697-710 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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10 |
Material Type: Artigo
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FPGA Based on Integration of CMOS and RRAMTanachutiwat, S. ; Ming Liu ; Wei WangIEEE transactions on very large scale integration (VLSI) systems, 2011-11, Vol.19 (11), p.2023-2032 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |