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Refinado por: Nome da Publicação: Ieee Transactions On Computers remover idioma: Japonês remover
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11
In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping
In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping
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In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping

Zabihi, Masoud ; Chowdhury, Zamshed Iqbal ; Zhao, Zhengyang ; Karpuzcu, Ulya R. ; Wang, Jian-Ping ; Sapatnekar, Sachin S.

IEEE transactions on computers, 2019-08, Vol.68 (8), p.1159-1173 [Periódico revisado por pares]

IEEE

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12
DRAM Refresh Mechanisms, Penalties, and Trade-Offs
DRAM Refresh Mechanisms, Penalties, and Trade-Offs
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DRAM Refresh Mechanisms, Penalties, and Trade-Offs

Bhati, Ishwar ; Mu-Tien Chang ; Chishti, Zeshan ; Shih-Lien Lu ; Jacob, Bruce

IEEE transactions on computers, 2016-01, Vol.65 (1), p.108-121 [Periódico revisado por pares]

IEEE

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13
A systematic approach to exploring embedded system architectures at multiple abstraction levels
A systematic approach to exploring embedded system architectures at multiple abstraction levels
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A systematic approach to exploring embedded system architectures at multiple abstraction levels

Pimentel, A.D. ; Erbas, C. ; Polstra, S.

IEEE transactions on computers, 2006-02, Vol.55 (2), p.99-112 [Periódico revisado por pares]

New York: IEEE

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14
Performance evaluation and design trade-offs for network-on-chip interconnect architectures
Performance evaluation and design trade-offs for network-on-chip interconnect architectures
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Performance evaluation and design trade-offs for network-on-chip interconnect architectures

Partha Pratim Pande ; Grecu, C. ; Jones, M. ; Ivanov, A. ; Saleh, R.

IEEE transactions on computers, 2005-08, Vol.54 (8), p.1025-1040 [Periódico revisado por pares]

New York: IEEE

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15
HEAWS: An Accelerator for Homomorphic Encryption on the Amazon AWS FPGA
HEAWS: An Accelerator for Homomorphic Encryption on the Amazon AWS FPGA
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HEAWS: An Accelerator for Homomorphic Encryption on the Amazon AWS FPGA

Turan, Furkan ; Roy, Sujoy Sinha ; Verbauwhede, Ingrid

IEEE transactions on computers, 2020-08, Vol.69 (8), p.1185-1196 [Periódico revisado por pares]

IEEE

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16
A Multi-Resolution FPGA-Based Architecture for Real-Time Edge and Corner Detection
A Multi-Resolution FPGA-Based Architecture for Real-Time Edge and Corner Detection
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A Multi-Resolution FPGA-Based Architecture for Real-Time Edge and Corner Detection

Possa, Paulo Ricardo ; Mahmoudi, Sidi Ahmed ; Harb, Naim ; Valderrama, Carlos ; Manneback, Pierre

IEEE transactions on computers, 2014-10, Vol.63 (10), p.2376-2388 [Periódico revisado por pares]

New York: IEEE

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17
RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme
RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme
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RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme

Ching-Yi Chen ; Hsiu-Chuan Shih ; Cheng-Wen Wu ; Chih-He Lin ; Pi-Feng Chiu ; Shyh-Shyuan Sheu ; Chen, Frederick T.

IEEE transactions on computers, 2015-01, Vol.64 (1), p.180-190 [Periódico revisado por pares]

New York: IEEE

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18
Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads
Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads
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Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads

Zaruba, Florian ; Schuiki, Fabian ; Hoefler, Torsten ; Benini, Luca

IEEE transactions on computers, 2021-11, Vol.70 (11), p.1845-1860 [Periódico revisado por pares]

IEEE

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19
Elliptic Curve Cryptography Point Multiplication Core for Hardware Security Module
Elliptic Curve Cryptography Point Multiplication Core for Hardware Security Module
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Elliptic Curve Cryptography Point Multiplication Core for Hardware Security Module

Mehrabi, Mohamad Ali ; Doche, Christophe ; Jolfaei, Alireza

IEEE transactions on computers, 2020-11, Vol.69 (11), p.1707-1718 [Periódico revisado por pares]

IEEE

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20
Built-in Security Computer: Deploying Security-First Architecture Using Active Security Processor
Built-in Security Computer: Deploying Security-First Architecture Using Active Security Processor
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Built-in Security Computer: Deploying Security-First Architecture Using Active Security Processor

Meng, Dan ; Hou, Rui ; Shi, Gang ; Tu, Bibo ; Yu, Aimin ; Zhu, Ziyuan ; Jia, Xiaoqi ; Wen, Yu ; Yang, Yun

IEEE transactions on computers, 2020-11, Vol.69 (11), p.1571-1583 [Periódico revisado por pares]

IEEE

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