Result Number | Material Type | Add to My Shelf Action | Record Details and Options |
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1 |
Material Type: Artigo
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Heuristics for Area Minimization in LUT-Based FPGA Technology MappingManohararajah, V. ; Brown, S.D. ; Vranesic, Z.G.IEEE transactions on computer-aided design of integrated circuits and systems, 2006-11, Vol.25 (11), p.2331-2340 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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2 |
Material Type: Artigo
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Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit designShi, C.-J.R. ; Xiang-Dong TanIEEE transactions on computer-aided design of integrated circuits and systems, 2001-07, Vol.20 (7), p.813-827 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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3 |
Material Type: Artigo
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Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemCTianhao Zhang ; Chakrabarty, K. ; Fair, R.B.IEEE transactions on computer-aided design of integrated circuits and systems, 2004-06, Vol.23 (6), p.843-858 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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4 |
Material Type: Artigo
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On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuitsTakahashi, H. ; Boateng, K.O. ; Saluja, K.K. ; Takamatsu, Y.IEEE transactions on computer-aided design of integrated circuits and systems, 2002-03, Vol.21 (3), p.362-368 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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5 |
Material Type: Artigo
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Error bound for reduced system model by Pade approximation via the Lanczos processZhaojun Bai ; Slone, R.D. ; Smith, W.T. ; Qiang YeIEEE transactions on computer-aided design of integrated circuits and systems, 1999-02, Vol.18 (2), p.133-141 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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6 |
Material Type: Artigo
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Minimizing production test time to detect faults in analog circuitsMilor, L. ; Sangiovanni-Vincentelli, A.L.IEEE transactions on computer-aided design of integrated circuits and systems, 1994, Vol.13 (6), p.796-813 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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7 |
Material Type: Artigo
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On Delay Fault Testing in Logic CircuitsChin Jen Lin ; Reddy, S.M.IEEE transactions on computer-aided design of integrated circuits and systems, 1987-09, Vol.6 (5), p.694-703 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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8 |
Material Type: Artigo
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Electrical analysis and modeling of floating-gate faultRenovell, M. ; Cambon, G.N.IEEE transactions on computer-aided design of integrated circuits and systems, 1992-11, Vol.11 (11), p.1450-1458 [Periódico revisado por pares]NEW YORK: IEEETexto completo disponível |
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9 |
Material Type: Artigo
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Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devicesDiaz, C.H. ; Sung-Mo Kang ; Duvvury, C.IEEE transactions on computer-aided design of integrated circuits and systems, 1994, Vol.13 (4), p.482-493 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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10 |
Material Type: Artigo
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A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faultsGharaybeh, M.A. ; Bushnell, M.L. ; Agrawal, V.D.IEEE transactions on computer-aided design of integrated circuits and systems, 1998-09, Vol.17 (9), p.873-876 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |