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1
Software-based self-testing methodology for processor cores
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Software-based self-testing methodology for processor cores

Li Chen ; Dey, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-03, Vol.20 (3), p.369-380 [Periódico revisado por pares]

New York: IEEE

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2
A compiler-based approach for dynamically managing scratch-pad memories in embedded systems
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A compiler-based approach for dynamically managing scratch-pad memories in embedded systems

Kandemir, M. ; Ramanujam, J. ; Irwin, M.J. ; Vijaykrishnan, N. ; Kadayif, I. ; Parikh, A.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-02, Vol.23 (2), p.243-260 [Periódico revisado por pares]

New York: IEEE

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3
Analysis and synthesis of weighted-sum functions
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Analysis and synthesis of weighted-sum functions

Sasao, T.

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-05, Vol.25 (5), p.789-796 [Periódico revisado por pares]

New York: IEEE

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4
Path delay fault diagnosis in combinational circuits with implicit fault enumeration
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Artigo
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Path delay fault diagnosis in combinational circuits with implicit fault enumeration

Pant, P. ; Yuan-Chieh Hsu ; Gupta, S.K. ; Chatterjee, A.

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-10, Vol.20 (10), p.1226-1235, Article 1226 [Periódico revisado por pares]

New York: IEEE

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