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Run-time neuro-fuzzy type-2 controller for power optimisation of GP-GPU architecture
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Run-time neuro-fuzzy type-2 controller for power optimisation of GP-GPU architecture

Najam, Shaheryar ; Ahmed, Jameel

IET circuits, devices & systems, 2020-11, Vol.14 (8), p.1253-1257 [Periódico revisado por pares]

The Institution of Engineering and Technology

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LTE/LTE-A signal compression on the CPRI interface
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LTE/LTE-A signal compression on the CPRI interface

Bin Guo ; Wei Cao ; An Tao ; Samardzija, Dragan

Bell Labs technical journal, 2013-09, Vol.18 (2), p.117-133 [Periódico revisado por pares]

Murray Hill: IEEE

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3
Multiple sampling PSC-PWM with hierarchical control architecture for MMC-DSTATCOM
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Multiple sampling PSC-PWM with hierarchical control architecture for MMC-DSTATCOM

Zhang, Yuxiao ; Dai, Ke ; Xu, Chen ; Kang, Yong ; Dai, Ziwei

IET electric power applications, 2019-10, Vol.13 (10), p.1431-1440 [Periódico revisado por pares]

The Institution of Engineering and Technology

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Implementation of a low-power LVQ architecture on FPGA
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Implementation of a low-power LVQ architecture on FPGA

Chalbi, Najoua ; Boubaker, Mohamed ; Hedi Bedoui, Mohamed

IET circuits, devices & systems, 2017-11, Vol.11 (6), p.597-604 [Periódico revisado por pares]

The Institution of Engineering and Technology

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5
Decentralised resilient autonomous control architecture for dynamic microgrids
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Decentralised resilient autonomous control architecture for dynamic microgrids

Bani-Ahmed, Abedalsalam ; Rashidi, Mohammed ; Nasiri, Adel

IET generation, transmission & distribution, 2019-06, Vol.13 (11), p.2182-2189 [Periódico revisado por pares]

The Institution of Engineering and Technology

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6
RIBM3DU‐Net: Glioma tumour substructures segmentation in magnetic resonance images using residual‐inception block with modified 3D U‐Net architecture
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RIBM3DU‐Net: Glioma tumour substructures segmentation in magnetic resonance images using residual‐inception block with modified 3D U‐Net architecture

Shajahan, Syedsafi ; Pathmanaban, Sriramakrishnan ; Tiruvenkadam, Kalaiselvi

International journal of imaging systems and technology, 2024-03, Vol.34 (2), p.n/a [Periódico revisado por pares]

Hoboken, USA: John Wiley & Sons, Inc

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7
Simplified merged processing element for successive-cancellation polar decoder
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Simplified merged processing element for successive-cancellation polar decoder

Yun, H.-R ; Lee, H

Electronics letters, 2016-02, Vol.52 (4), p.270-272 [Periódico revisado por pares]

The Institution of Engineering and Technology

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8
The Principle and Progress of Dynamically Reconfigurable Computing Technologies
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The Principle and Progress of Dynamically Reconfigurable Computing Technologies

Wei, Shaojun ; Lu, Yan'an

Chinese Journal of Electronics, 2020-07, Vol.29 (4), p.595-607 [Periódico revisado por pares]

Published by the IET on behalf of the CIE

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9
Digital predistortion architecture with reduced ADC dynamic range
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Digital predistortion architecture with reduced ADC dynamic range

Liu, Ying ; Quan, Xin ; Shao, Shihai ; Tang, Youxi

Electronics letters, 2016-03, Vol.52 (6), p.435-437 [Periódico revisado por pares]

The Institution of Engineering and Technology

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10
Making smart use of excess antennas: Massive MIMO, small cells, and TDD
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Making smart use of excess antennas: Massive MIMO, small cells, and TDD

Hoydis, Jakob ; Hosseini, Kianoush ; ten Brink, Stephan ; Debbah, Mérouane

Bell Labs technical journal, 2013-09, Vol.18 (2), p.5-21 [Periódico revisado por pares]

Murray Hill: IEEE

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