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1
On the Need for Passive Monitoring in Sensor Networks
On the Need for Passive Monitoring in Sensor Networks
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Ata de Congresso 		Adicionar ao Meu Espaço

On the Need for Passive Monitoring in Sensor Networks

Awad, A. ; Nebel, R. ; German, R. ; Dressler, F.

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008, p.693-699

IEEE

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2
An FPGA Implementation of a Quadruple-Based Multiplier for 4D Clifford Algebra
An FPGA Implementation of a Quadruple-Based Multiplier for 4D Clifford Algebra
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

An FPGA Implementation of a Quadruple-Based Multiplier for 4D Clifford Algebra

Franchini, S. ; Gentile, A. ; Sorbello, F. ; Vassallo, G. ; Vitabile, S.

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008, p.743-751

IEEE

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3
Design of a High Performance Traffic Generator on Network Processor
Design of a High Performance Traffic Generator on Network Processor
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

Design of a High Performance Traffic Generator on Network Processor

Antichi, G. ; Di Pietro, A. ; Ficara, D. ; Giordano, S. ; Procissi, G. ; Vitucci, F.

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008, p.438-441

IEEE

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4
Design of a Distributed Embedded System for Domotic Applications
Design of a Distributed Embedded System for Domotic Applications
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

Design of a Distributed Embedded System for Domotic Applications

Sechi, F. ; Fanucci, L. ; Luschi, S. ; Perini, S. ; Madesani, M.

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008, p.427-431

IEEE

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5
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism

Schaffer, R. ; Merker, R. ; Hannig, F. ; Teich, J.

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008, p.391-398

IEEE

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6
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures

Wolinski, C. ; Kuchcinski, K. ; Teich, J. ; Hannig, F.

11th Euromicro conference on Digital System Design (DSD),Parma, Italy,2008-09-03 - 2008-09-05, 2008, p.345-352

IEEE

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