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Simultaneous Scheduling and Core-Type Optimization for Moldable Fork-Join Tasks on Heterogeneous Multicores
Simultaneous Scheduling and Core-Type Optimization for Moldable Fork-Join Tasks on Heterogeneous Multicores
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Simultaneous Scheduling and Core-Type Optimization for Moldable Fork-Join Tasks on Heterogeneous Multicores

NISHIKAWA, Hiroki ; SHIMADA, Kana ; TANIGUCHI, Ittetsu ; TOMIYAMA, Hiroyuki

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2022/03/01, Vol.E105.A(3), pp.540-548 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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Adaptive Channel Scheduling for Acceleration and Fine Control of RNN-Based Image Compression
Adaptive Channel Scheduling for Acceleration and Fine Control of RNN-Based Image Compression
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Adaptive Channel Scheduling for Acceleration and Fine Control of RNN-Based Image Compression

KIM, Sang Hoon ; KO, Jong Hwan

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2023/09/01, Vol.E106.A(9), pp.1211-1215 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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3
Convergence Acceleration via Chebyshev Step: Plausible Interpretation of Deep-Unfolded Gradient Descent
Convergence Acceleration via Chebyshev Step: Plausible Interpretation of Deep-Unfolded Gradient Descent
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Convergence Acceleration via Chebyshev Step: Plausible Interpretation of Deep-Unfolded Gradient Descent

TAKABE, Satoshi ; WADAYAMA, Tadashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2022/08/01, Vol.E105.A(8), pp.1110-1120 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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4
Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework
Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework
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Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework

YOSHIYA, Eiji ; NAKANISHI, Tomoya ; ISSHIKI, Tsuyoshi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2022/07/01, Vol.E105.A(7), pp.1061-1069 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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5
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation
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Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation

HATTORI, Naoki ; SHIOMI, Jun ; MASUDA, Yutaka ; ISHIHARA, Tohru ; SHINYA, Akihiko ; NOTOMI, Masaya

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2021/11/01, Vol.E104.A(11), pp.1477-1487 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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6
High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA
High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA
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High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA

RANAWAKA, Piyumal ; EKPANYAPONG, Mongkol ; TAVARES, Adriano ; DAILEY, Mathew ; ATHIKULWONGSE, Krit ; SILVA, Vitor

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2019/12/01, Vol.E102.A(12), pp.1792-1803 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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7
Deep Network for Parametric Bilinear Generalized Approximate Message Passing and Its Application in Compressive Sensing under Matrix Uncertainty
Deep Network for Parametric Bilinear Generalized Approximate Message Passing and Its Application in Compressive Sensing under Matrix Uncertainty
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Deep Network for Parametric Bilinear Generalized Approximate Message Passing and Its Application in Compressive Sensing under Matrix Uncertainty

SI, Jingjing ; SUN, Wenwen ; LI, Chuang ; CHENG, Yinbo

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2021/04/01, Vol.E104.A(4), pp.751-756 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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8
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing
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On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing

XU, Hongjie ; SHIOMI, Jun ; ISHIHARA, Tohru ; ONODERA, Hidetoshi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2019/12/01, Vol.E102.A(12), pp.1741-1750 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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9
Realizability of Choreography Given by Two Scenarios
Realizability of Choreography Given by Two Scenarios
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Realizability of Choreography Given by Two Scenarios

KINOSHITA, Toshiki ; MIYAMOTO, Toshiyuki

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2018/02/01, Vol.E101.A(2), pp.345-356 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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10
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
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Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble

MITSUNARI, Koichi ; YU, Jaehoon ; ONOYE, Takao ; HASHIMOTO, Masanori

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2018/09/01, Vol.E101.A(9), pp.1298-1307 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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