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Design and Implementation of a Service-Oriented Architecture for the Optimization of Industrial Applications
Design and Implementation of a Service-Oriented Architecture for the Optimization of Industrial Applications
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Design and Implementation of a Service-Oriented Architecture for the Optimization of Industrial Applications

Girbea, Alina ; Suciu, Constantin ; Nechifor, Septimiu ; Sisak, Francisc

IEEE transactions on industrial informatics, 2014-02, Vol.10 (1), p.185-196

Piscataway: IEEE

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2
An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures
An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures
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An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures

Zulehner, Alwin ; Paler, Alexandru ; Wille, Robert

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-07, Vol.38 (7), p.1226-1236 [Periódico revisado por pares]

New York: IEEE

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3
Risk-5: Controlled Approximations for RISC-V
Risk-5: Controlled Approximations for RISC-V
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Risk-5: Controlled Approximations for RISC-V

Felzmann, Isaias ; Filho, Joao Fabricio ; Wanner, Lucas

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-11, Vol.39 (11), p.4052-4063 [Periódico revisado por pares]

New York: IEEE

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4
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers
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An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers

Cong, Jason ; Li, Peng ; Xiao, Bingjun ; Zhang, Peng

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-03, Vol.35 (3), p.407-418 [Periódico revisado por pares]

New York: IEEE

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5
Hardware/Software Co-Exploration of Neural Architectures
Hardware/Software Co-Exploration of Neural Architectures
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Hardware/Software Co-Exploration of Neural Architectures

Jiang, Weiwen ; Yang, Lei ; Sha, Edwin Hsing-Mean ; Zhuge, Qingfeng ; Gu, Shouzhen ; Dasgupta, Sakyasingha ; Shi, Yiyu ; Hu, Jingtong

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4805-4815 [Periódico revisado por pares]

IEEE

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6
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
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Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks

Zhang, Chen ; Sun, Guangyu ; Fang, Zhenman ; Zhou, Peipei ; Pan, Peichen ; Cong, Jason

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-11, Vol.38 (11), p.2072-2085 [Periódico revisado por pares]

New York: IEEE

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7
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
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NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

Chen, Pai-Yu ; Peng, Xiaochen ; Yu, Shimeng

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3067-3080 [Periódico revisado por pares]

New York: IEEE

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8
Pixels to Classes: Intelligent Learning Framework for Multiclass Skin Lesion Localization and Classification
Pixels to Classes: Intelligent Learning Framework for Multiclass Skin Lesion Localization and Classification
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Pixels to Classes: Intelligent Learning Framework for Multiclass Skin Lesion Localization and Classification

Khan, Muhammad Attique ; Zhang, Yu-Dong ; Sharif, Muhammad ; Akram, Tallha

Computers & electrical engineering, 2021-03, Vol.90, p.106956, Article 106956 [Periódico revisado por pares]

Amsterdam: Elsevier Ltd

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9
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA
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DLAU: A Scalable Deep Learning Accelerator Unit on FPGA

Wang, Chao ; Gong, Lei ; Yu, Qi ; Li, Xi ; Xie, Yuan ; Zhou, Xuehai

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-03, Vol.36 (3), p.513-517 [Periódico revisado por pares]

New York: IEEE

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10
LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults
LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults
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LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Ni, Tianming ; Yao, Yao ; Chang, Hao ; Lu, Lin ; Liang, Huaguo ; Yan, Aibin ; Huang, Zhengfeng ; Wen, Xiaoqing

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2938-2951 [Periódico revisado por pares]

New York: IEEE

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