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SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems
SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems
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SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems

Pomante, Luigi ; Muttillo, Vittoriano ; Santic, Marco ; Serri, Paolo

Microprocessors and microsystems, 2020-02, Vol.72, p.102898, Article 102898 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension
A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension
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A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension

Patsidis, Karyofyllis ; Konstantinou, Dimitris ; Nicopoulos, Chrysostomos ; Dimitrakopoulos, Giorgos

Microprocessors and microsystems, 2018-09, Vol.61, p.1-10 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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3
Fitting processor architectures for measurement-based probabilistic timing analysis
Fitting processor architectures for measurement-based probabilistic timing analysis
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Fitting processor architectures for measurement-based probabilistic timing analysis

Kosmidis, Leonidas ; Quiñones, Eduardo ; Abella, Jaume ; Vardanega, Tullio ; Hernandez, Carles ; Gianarro, Andrea ; Broster, Ian ; Cazorla, Francisco J.

Microprocessors and microsystems, 2016-11, Vol.47, p.287-302 [Periódico revisado por pares]

Elsevier B.V

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4
Supporting concurrent memory access in TCF processor architectures
Supporting concurrent memory access in TCF processor architectures
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Supporting concurrent memory access in TCF processor architectures

Forsell, Martti ; Roivainen, Jussi ; Leppänen, Ville ; Träff, Jesper Larsson

Microprocessors and microsystems, 2018-11, Vol.63, p.226-236 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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5
Dynamically adaptive register file architecture for energy reduction in embedded processors
Dynamically adaptive register file architecture for energy reduction in embedded processors
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Dynamically adaptive register file architecture for energy reduction in embedded processors

Khavari Tavana, Mohammad ; Ahmadian Khameneh, Saba ; Goudarzi, Maziar

Microprocessors and microsystems, 2015-03, Vol.39 (2), p.49-63 [Periódico revisado por pares]

Elsevier B.V

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6
Design and simulation of a sensorless permanent magnet synchronous motor drive with microprocessor-based PI controller and dedicated hardware EKF estimator
Design and simulation of a sensorless permanent magnet synchronous motor drive with microprocessor-based PI controller and dedicated hardware EKF estimator
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Design and simulation of a sensorless permanent magnet synchronous motor drive with microprocessor-based PI controller and dedicated hardware EKF estimator

Kung, Ying-Shieh ; Thanh, Nguyen Phan ; Wang, Ming-Shyng

Applied mathematical modelling, 2015-10, Vol.39 (19), p.5816-5827 [Periódico revisado por pares]

Elsevier Inc

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7
Side-channel leakage models for RISC instruction set architectures from empirical data
Side-channel leakage models for RISC instruction set architectures from empirical data
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Side-channel leakage models for RISC instruction set architectures from empirical data

Seuschek, Hermann ; Rass, Stefan

Microprocessors and microsystems, 2016-11, Vol.47, p.74-81 [Periódico revisado por pares]

Elsevier B.V

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8
State of art innovative technique for management of scratchpad memory (scratch)
State of art innovative technique for management of scratchpad memory (scratch)
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State of art innovative technique for management of scratchpad memory (scratch)

Tabbassum, Kavita ; Talpur, Shahnawaz ; Khahro, Shahnwaz Farhan

Microprocessors and microsystems, 2019-10, Vol.70, p.31-37 [Periódico revisado por pares]

Kidlington: Elsevier B.V

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9
Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding
Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding
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Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding

Jan, Yahya ; Jóźwiak, Lech

Microprocessors and microsystems, 2014-03, Vol.38 (2), p.152-169 [Periódico revisado por pares]

Elsevier B.V

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10
Special purpose processor for parameter identification of CNC second order servo systems on a low-cost FPGA platform
Special purpose processor for parameter identification of CNC second order servo systems on a low-cost FPGA platform
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Special purpose processor for parameter identification of CNC second order servo systems on a low-cost FPGA platform

Morales-Velazquez, Luis ; Romero-Troncoso, Rene de Jesus ; Osornio-Rios, Roque Alfredo ; Herrera-Ruiz, Gilberto ; Jesus de Santiago-Perez, J.

Mechatronics (Oxford), 2010-03, Vol.20 (2), p.265-272 [Periódico revisado por pares]

Oxford: Elsevier Ltd

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