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1
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
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Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

Ma, Yufei ; Cao, Yu ; Vrudhula, Sarma ; Seo, Jae-sun

IEEE transactions on very large scale integration (VLSI) systems, 2018-07, Vol.26 (7), p.1354-1367 [Periódico revisado por pares]

New York: IEEE

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A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
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A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection

Nguyen, Duy Thanh ; Nguyen, Tuan Nghia ; Kim, Hyun ; Lee, Hyuk-Jae

IEEE transactions on very large scale integration (VLSI) systems, 2019-08, Vol.27 (8), p.1861-1873 [Periódico revisado por pares]

New York: IEEE

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3
Hardware/Software Co-Exploration of Neural Architectures
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Hardware/Software Co-Exploration of Neural Architectures

Jiang, Weiwen ; Yang, Lei ; Sha, Edwin Hsing-Mean ; Zhuge, Qingfeng ; Gu, Shouzhen ; Dasgupta, Sakyasingha ; Shi, Yiyu ; Hu, Jingtong

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4805-4815 [Periódico revisado por pares]

IEEE

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4
FPGA-Based High-Throughput CNN Hardware Accelerator With High Computing Resource Utilization Ratio
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FPGA-Based High-Throughput CNN Hardware Accelerator With High Computing Resource Utilization Ratio

Huang, Wenjin ; Wu, Huangtao ; Chen, Qingkun ; Luo, Conghui ; Zeng, Shihao ; Li, Tianrui ; Huang, Yihua

IEEE transaction on neural networks and learning systems, 2022-08, Vol.33 (8), p.4069-4083

United States: IEEE

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5
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review
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FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

Shawahna, Ahmad ; Sait, Sadiq M. ; El-Maleh, Aiman

IEEE access, 2019, Vol.7, p.7823-7859 [Periódico revisado por pares]

Piscataway: IEEE

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6
A Survey of System Architectures and Techniques for FPGA Virtualization
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A Survey of System Architectures and Techniques for FPGA Virtualization

Quraishi, Masudul Hassan ; Tavakoli, Erfan Bank ; Ren, Fengbo

IEEE transactions on parallel and distributed systems, 2021-09, Vol.32 (9), p.2216-2230 [Periódico revisado por pares]

IEEE

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7
Encoding, Model, and Architecture: Systematic Optimization for Spiking Neural Network in FPGAs
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Encoding, Model, and Architecture: Systematic Optimization for Spiking Neural Network in FPGAs

Fang, Haowen ; Mei, Zaidao ; Shrestha, Amar ; Zhao, Ziyi ; Li, Yilan ; Qiu, Qinru

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9

Association on Computer Machinery

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8
Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines
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Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines

Kyrkou, Christos ; Bouganis, Christos-Savvas ; Theocharides, Theocharis ; Polycarpou, Marios M.

IEEE transaction on neural networks and learning systems, 2016-01, Vol.27 (1), p.99-112

United States: IEEE

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9
A cloud-scale acceleration architecture
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A cloud-scale acceleration architecture

Caulfield, Adrian M. ; Chung, Eric S. ; Putnam, Andrew ; Angepat, Hari ; Fowers, Jeremy ; Haselman, Michael ; Heil, Stephen ; Humphrey, Matt ; Kaur, Puneet ; Joo-Young Kim ; Lo, Daniel ; Massengill, Todd ; Ovtcharov, Kalin ; Papamichael, Michael ; Woods, Lisa ; Lanka, Sitaram ; Chiou, Derek ; Burger, Doug

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2016, p.1-13

IEEE

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10
Plasticine: A Reconfigurable Accelerator for Parallel Patterns
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Plasticine: A Reconfigurable Accelerator for Parallel Patterns

Prabhakar, Raghu ; Zhang, Yaqi ; Koeplinger, David ; Feldman, Matt ; Zhao, Tian ; Hadjis, Stefan ; Pedram, Ardavan ; Kozyrakis, Christos ; Olukotun, Kunle

IEEE MICRO, 2018-05, Vol.38 (3), p.20-31 [Periódico revisado por pares]

Los Alamitos: IEEE

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