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1
Scene Recognition by Manifold Regularized Deep Learning Architecture
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Scene Recognition by Manifold Regularized Deep Learning Architecture

Yuan, Yuan ; Mou, Lichao ; Lu, Xiaoqiang

IEEE transaction on neural networks and learning systems, 2015-10, Vol.26 (10), p.2222-2233

United States: IEEE

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2
On the Complexity of Neural Network Classifiers: A Comparison Between Shallow and Deep Architectures
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On the Complexity of Neural Network Classifiers: A Comparison Between Shallow and Deep Architectures

Bianchini, Monica ; Scarselli, Franco

IEEE transaction on neural networks and learning systems, 2014-08, Vol.25 (8), p.1553-1565

New York, NY: IEEE

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3
SCANN: Synthesis of Compact and Accurate Neural Networks
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SCANN: Synthesis of Compact and Accurate Neural Networks

Hassantabar, Shayan ; Wang, Zeyu ; Jha, Niraj K.

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.3012-3025 [Periódico revisado por pares]

New York: IEEE

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4
OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks
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OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks

Yu, Yunxuan ; Wu, Chen ; Zhao, Tiandong ; Wang, Kun ; He, Lei

IEEE transactions on very large scale integration (VLSI) systems, 2020-01, Vol.28 (1), p.35-47 [Periódico revisado por pares]

New York: IEEE

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5
Efficient Online Learning Algorithms Based on LSTM Neural Networks
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Efficient Online Learning Algorithms Based on LSTM Neural Networks

Ergen, Tolga ; Kozat, Suleyman Serdar

IEEE transaction on neural networks and learning systems, 2018-08, Vol.29 (8), p.3772-3783

United States: IEEE

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6
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
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NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

Chen, Pai-Yu ; Peng, Xiaochen ; Yu, Shimeng

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3067-3080 [Periódico revisado por pares]

New York: IEEE

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7
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture
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High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture

Kala, S. ; Jose, Babita R. ; Mathew, Jimson ; Nalesh, S.

IEEE transactions on very large scale integration (VLSI) systems, 2019-12, Vol.27 (12), p.2816-2828 [Periódico revisado por pares]

New York: IEEE

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8
A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing
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A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing

Wang, Jingcheng ; Wang, Xiaowei ; Eckert, Charles ; Subramaniyan, Arun ; Das, Reetuparna ; Blaauw, David ; Sylvester, Dennis

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.76-86 [Periódico revisado por pares]

New York: IEEE

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9
Subarchitecture Ensemble Pruning in Neural Architecture Search
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Subarchitecture Ensemble Pruning in Neural Architecture Search

Bian, Yijun ; Song, Qingquan ; Du, Mengnan ; Yao, Jun ; Chen, Huanhuan ; Hu, Xia

IEEE transaction on neural networks and learning systems, 2022-12, Vol.33 (12), p.7928-7936

United States: IEEE

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10
DRINet for Medical Image Segmentation
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DRINet for Medical Image Segmentation

Chen, Liang ; Bentley, Paul ; Mori, Kensaku ; Misawa, Kazunari ; Fujiwara, Michitaka ; Rueckert, Daniel

IEEE transactions on medical imaging, 2018-11, Vol.37 (11), p.2453-2462

United States: IEEE

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