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A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation
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A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

Kang, Ji-Hyo ; Yang, Jaehyeok ; Kim, Kyunghoon ; Chae, Joo-Hyung ; Lee, Gangsik ; Byeon, Sangyeon ; Kim, Boram ; Kim, Dong-Hyun ; Kim, Youngtaek ; Cho, Yeongmuk ; Ji, Junghwan ; Jeong, Sera ; Cha, Jaehoon ; Park, Minsoo ; Kim, Hongdeuk ; Park, Sijun ; Kim, Sunho ; Jung, Hae-Kang ; Jang, Jieun ; Lee, Sangkwon ; Kim, Hyungsoo ; Cho, Joo-Hwan ; Chun, Junhyun ; Cha, Seonyong

IEEE journal of solid-state circuits, 2022-01, Vol.57 (1), p.212-223 [Periódico revisado por pares]

New York: IEEE

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2
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ
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A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ

Lee, Daewoong ; Baek, Jaehyeok ; Kwon, Hye-Jung ; Kwon, Dae-Hyun ; Cho, Chulhee ; Kim, Sang-Hoon ; An, Donggun ; Chang, Chulsoon ; Lim, Unhak ; Im, Jiyeon ; Sung, Wonju ; Kim, Hye-Ran ; Park, Sun-Young ; Kim, Hyoung-Joo ; Seol, Hoseok ; Kim, Juhwan ; Shin, Jungbum ; Kang, Gil-Young ; Kim, Yong-Hun ; Kim, Sooyoung ; Park, Wansoo ; Kim, Seok-Jung ; Lee, Chan-Yong ; Lee, Seungseob ; Park, Tae-Hoon ; Oh, Chi-Sung ; Ban, Hyodong ; Ko, Hyungjong ; Song, Hoyoung ; Oh, Tae-Young ; Hwang, Sang-Joon ; Oh, Kyung-Suk ; Choi, Jung-Hwan ; Lee, Jooyoung

IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.1-12 [Periódico revisado por pares]

New York: IEEE

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3
D-buffer: irregular image data storage made practical
D-buffer: irregular image data storage made practical
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D-buffer: irregular image data storage made practical

Lipowski, J. K.

Opto-electronics review, 2013, Vol.21 (1), p.103-125 [Periódico revisado por pares]

Heidelberg: SP Versita

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4
Hybrid stacked neural network empowered by novel loss function for structural response history prediction using input excitation and roof acceleration
Hybrid stacked neural network empowered by novel loss function for structural response history prediction using input excitation and roof acceleration
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Hybrid stacked neural network empowered by novel loss function for structural response history prediction using input excitation and roof acceleration

Karami, Reza ; Yazdanpanah, Omid ; Dolatshahi, Kiarash M. ; Chang, Minwoo

Engineering applications of artificial intelligence, 2024-10, Vol.136, p.108984, Article 108984 [Periódico revisado por pares]

Elsevier Ltd

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5
Low Power 260k Color TFT LCD Driver IC
Low Power 260k Color TFT LCD Driver IC
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Low Power 260k Color TFT LCD Driver IC

Kim, Bo‐Sung ; Ko, Jae‐Su ; Lee, Won‐Hyo ; Park, Kyoung‐Won ; Hong, Soon‐Yang

ETRI journal, 2003-10, Vol.25 (5), p.288-296 [Periódico revisado por pares]

Taejon: Electronics and Telecommunications Research Institute

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6
Evaluation of Two Parallel Finite Element Implementations of the Time-Dependent Advection Diffusion Problem: GPU versus Cluster Considering Time and Energy Consumption
Evaluation of Two Parallel Finite Element Implementations of the Time-Dependent Advection Diffusion Problem: GPU versus Cluster Considering Time and Energy Consumption
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Evaluation of Two Parallel Finite Element Implementations of the Time-Dependent Advection Diffusion Problem: GPU versus Cluster Considering Time and Energy Consumption

De Souza, Alberto F. ; Veronese, Lucas ; Lima, Leonardo M. ; Badue, Claudine ; Catabriga, Lucia Nakajima, Kengo ; Marques, Osni ; Daydé, Michel

High Performance Computing for Computational Science - VECPAR 2012, p.149-162 [Periódico revisado por pares]

Berlin, Heidelberg: Springer Berlin Heidelberg

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7
Trends in high-speed DRAM architectures
Trends in high-speed DRAM architectures
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Trends in high-speed DRAM architectures

Kumanoya, Masaki ; Ogawa, Toshiyuki ; Konishi, Yasuhiro ; Dosaka, Katsumi ; Shimotori, Kazuhiro

IEICE transactions on electronics, 1996, Vol.E79-C (4), p.472-481 [Periódico revisado por pares]

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8
Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems
Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems
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Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems

O'Connor, Mike ; Chatterjee, Niladrish ; Lee, Donghyuk ; Wilson, John ; Agrawal, Aditya ; Keckler, Stephen W. ; Dally, William J.

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, p.41-54

New York, NY, USA: ACM

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9
ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration
ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration
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ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration

Long, Yun ; Na, Taesik ; Mukhopadhyay, Saibal

IEEE transactions on very large scale integration (VLSI) systems, 2018-12, Vol.26 (12), p.2781-2794 [Periódico revisado por pares]

New York: IEEE

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10
TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs
TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs
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TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs

Zhang, Yicong ; Wang, Mingyu ; Mai, Yangzhan ; Yu, Zhiyi

IEEE transactions on very large scale integration (VLSI) systems, 2023-12, Vol.31 (12), p.2030-2043 [Periódico revisado por pares]

New York: IEEE

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