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Refinado por: autor: Gray, C remover Nome da Publicação: Ieee Journal of Solid-State Circuits remover
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Sampling technique and its cmos implementation with 1 gb / s bandwith and 25 ps resolution
Sampling technique and its cmos implementation with 1 gb / s bandwith and 25 ps resolution
Material Type:
Artigo 		Adicionar ao Meu Espaço

Sampling technique and its cmos implementation with 1 gb / s bandwith and 25 ps resolution

C T Gray W Liu; Wilhelmus Adrianus Maria Van Noije 1951-; A Hugues Junior; R K Cavin

New York v.29, n.3 , p.340-9, mar. 1994 Ieee Journal of Solid-State Circuits

New York 1994

Item não circula. Consulte sua biblioteca.(Acessar)

2
Sampling technique and its cmos implementation with 1 gb / s bandwith and 25 ps resolution
Sampling technique and its cmos implementation with 1 gb / s bandwith and 25 ps resolution
Material Type:
Artigo 		Adicionar ao Meu Espaço

Sampling technique and its cmos implementation with 1 gb / s bandwith and 25 ps resolution

C T Gray W Liu; Wilhelmus Adrianus Maria Van Noije 1951-; A Hugues Junior; R K Cavin

New York v.29, n.3 , p.340-9, mar. 1994 Ieee Journal of Solid-State Circuits

New York 1994

Item não circula. Consulte sua biblioteca.(Acessar)

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Deste Autor:

  1. Cavin, R
  2. Hugues Junior, A
  3. Liu, W
  4. Gray, C
  5. Van Noije, W

Neste Assunto:

  1. Circuitos Integrados

  • Realização: ABCD-USP USP   Logos de Redes Sociais: Freepik

Buscando em bases de dados remotas. Favor aguardar.