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Refinado por: Nome da Publicação: Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems remover Base de dados/Biblioteca: Science Citation Index Expanded (Web of Science) remover
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Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture
Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture
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Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

Wang, Boqian ; Lu, Zhonghai

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1523-1536 [Periódico revisado por pares]

New York: IEEE

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2
Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture
Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture
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Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture

Sun, Hanbo ; Zhu, Zhenhua ; Wang, Chenyu ; Ning, Xuefei ; Dai, Guohao ; Yang, Huazhong ; Wang, Yu

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1 [Periódico revisado por pares]

IEEE

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3
Specializing CGRAs for Light-Weight Convolutional Neural Networks
Specializing CGRAs for Light-Weight Convolutional Neural Networks
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Specializing CGRAs for Light-Weight Convolutional Neural Networks

Lee, Jungi ; Lee, Jongeun

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3387-3399 [Periódico revisado por pares]

New York: IEEE

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4
Exploring the Potential Benefits of Alternative Quantum Computing Architectures
Exploring the Potential Benefits of Alternative Quantum Computing Architectures
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Exploring the Potential Benefits of Alternative Quantum Computing Architectures

Deb, Arighna ; Dueck, Gerhard W. ; Wille, Robert

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-09, Vol.40 (9), p.1825-1835 [Periódico revisado por pares]

IEEE

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5
MCM-GPU Voltage Noise Characterization and Architecture-Level Mitigation
MCM-GPU Voltage Noise Characterization and Architecture-Level Mitigation
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MCM-GPU Voltage Noise Characterization and Architecture-Level Mitigation

Tan, Jingweijia ; Chen, Keyu ; Wang, Weiren ; Yan, Kaige ; Wei, Xiaohui

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1 [Periódico revisado por pares]

IEEE

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6
An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures
An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures
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An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures

Zulehner, Alwin ; Paler, Alexandru ; Wille, Robert

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-07, Vol.38 (7), p.1226-1236 [Periódico revisado por pares]

IEEE

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7
FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-based In-memory Computing
FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-based In-memory Computing
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FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-based In-memory Computing

Liu, Rui ; Zhang, Xiaoyu ; Xie, Zhiwen ; Wang, Xinyu ; Li, Zerun ; Chen, Xiaoming ; Han, Yinhe ; Tang, Minghua

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-09, Vol.42 (9), p.1-1 [Periódico revisado por pares]

IEEE

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8
SCANN: Synthesis of Compact and Accurate Neural Networks
SCANN: Synthesis of Compact and Accurate Neural Networks
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SCANN: Synthesis of Compact and Accurate Neural Networks

Hassantabar, Shayan ; Wang, Zeyu ; Jha, Niraj K.

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.3012-3025 [Periódico revisado por pares]

New York: IEEE

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9
Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture
Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture
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Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture

Wijtvliet, M. ; Kumar, A. ; Corporaal, H.

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.2915-2928 [Periódico revisado por pares]

IEEE

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10
Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond
Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond
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Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond

Luo, Xiangzhong ; Liu, Di ; Huai, Shuo ; Kong, Hao ; Chen, Hui ; Liu, Weichen

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-06, Vol.41 (6), p.1799-1812 [Periódico revisado por pares]

New York: IEEE

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