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Refinado por: Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover
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A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model
A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model
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A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model

Dang, Khanh N. ; Ben Ahmed, Akram ; Xuan-Tu Tran ; Okuyama, Yuichi ; Ben Abdallah, Abderazek

IEEE transactions on very large scale integration (VLSI) systems, 2017-11, Vol.25 (11), p.3099-3112 [Periódico revisado por pares]

IEEE

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2
VLSI architectural design tradeoffs for sliding-window log-MAP decoders
VLSI architectural design tradeoffs for sliding-window log-MAP decoders
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VLSI architectural design tradeoffs for sliding-window log-MAP decoders

WU, Chien-Ming ; SHIEH, Ming-Der ; WU, Chien-Hsing ; HWANG, Yin-Tsung ; CHEN, Jun-Hong

IEEE transactions on very large scale integration (VLSI) systems, 2005-04, Vol.13 (4), p.439-447 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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3
An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks
An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks
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An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks

Islam, Md Najrul ; Shrestha, Rahul ; Chowdhury, Shubhajit Roy

IEEE transactions on very large scale integration (VLSI) systems, 2022-12, Vol.30 (12), p.1-11 [Periódico revisado por pares]

New York: IEEE

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4
Knowledge-Based Neural Network Model for FPGA Logical Architecture Development
Knowledge-Based Neural Network Model for FPGA Logical Architecture Development
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Knowledge-Based Neural Network Model for FPGA Logical Architecture Development

Liu, Qiang ; Gao, Ming ; Zhang, Qijun

IEEE transactions on very large scale integration (VLSI) systems, 2016-02, Vol.24 (2), p.664-677 [Periódico revisado por pares]

New York: IEEE

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5
FLNA: Flexibly Accelerating Feature Learning Networks for Large-Scale Point Clouds With Efficient Dataflow Decoupling
FLNA: Flexibly Accelerating Feature Learning Networks for Large-Scale Point Clouds With Efficient Dataflow Decoupling
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FLNA: Flexibly Accelerating Feature Learning Networks for Large-Scale Point Clouds With Efficient Dataflow Decoupling

Lyu, Dongxu ; Li, Zhenyu ; Chen, Yuzhou ; Wang, Gang ; He, Weifeng ; Xu, Ningyi ; He, Guanghui

IEEE transactions on very large scale integration (VLSI) systems, 2024-04, Vol.32 (4), p.739-751 [Periódico revisado por pares]

New York: IEEE

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6
Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint
Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint
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Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint

Li Jiang ; Qiang Xu ; Chakrabarty, K. ; Mak, T. M.

IEEE transactions on very large scale integration (VLSI) systems, 2012-09, Vol.20 (9), p.1621-1633 [Periódico revisado por pares]

New York, NY: IEEE

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7
Area-Aware Cache Update Trackers for Postsilicon Validation
Area-Aware Cache Update Trackers for Postsilicon Validation
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Area-Aware Cache Update Trackers for Postsilicon Validation

Chandran, Sandeep ; Sarangi, Smruti R. ; Panda, Preeti Ranjan

IEEE transactions on very large scale integration (VLSI) systems, 2016-05, Vol.24 (5), p.1794-1807 [Periódico revisado por pares]

New York: IEEE

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8
A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic
A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic
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A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic

Abdel-Hafeez, S ; Gordon-Ross, A

IEEE transactions on very large scale integration (VLSI) systems, 2011-06, Vol.19 (6), p.1023-1033 [Periódico revisado por pares]

New York, NY: IEEE

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9
135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder
135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder
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135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder

LI, Gwo-Long ; CHEN, Tzu-Yu ; SHEN, Meng-Wei ; WEN, Meng-Hsun ; CHANG, Tian-Sheuan

IEEE transactions on very large scale integration (VLSI) systems, 2013-04, Vol.21 (4), p.636-647 [Periódico revisado por pares]

New York, NY: IEEE

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10
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer
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HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer

Liu, Shiwei ; Mu, Chen ; Jiang, Hao ; Wang, Yunzhengmao ; Zhang, Jinshan ; Lin, Feng ; Zhou, Keji ; Liu, Qi ; Chen, Chixiao

IEEE transactions on very large scale integration (VLSI) systems, 2024-02, Vol.32 (2), p.1-14 [Periódico revisado por pares]

New York: IEEE

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