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Refinado por: Nome da Publicação: Ieee Trans. Cad remover Nome da Publicação: Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems remover
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1
Optimality and scalability study of existing placement algorithms
Optimality and scalability study of existing placement algorithms
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Optimality and scalability study of existing placement algorithms

Chin-Chih Chang ; Cong, J. ; Romesis, M. ; Min Xie

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-04, Vol.23 (4), p.537-549 [Periódico revisado por pares]

New York: IEEE

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2
Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment
Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment
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Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment

Chunsheng Liu ; Chakrabarty, K.

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-05, Vol.22 (5), p.593-604 [Periódico revisado por pares]

New York: IEEE

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3
Synthesis of software programs for embedded control applications
Synthesis of software programs for embedded control applications
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Synthesis of software programs for embedded control applications

Balarin, F. ; Chiodo, M. ; Giusto, P. ; Hsieh, H. ; Jurecska, A. ; Lavagno, L. ; Sangiovanni-Vincentelli, A. ; Sentovich, E.M. ; Suzuki, K.

IEEE transactions on computer-aided design of integrated circuits and systems, 1999, Vol.18 (6), p.834-849 [Periódico revisado por pares]

New York, NY: IEEE

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4
Scan-based BIST fault diagnosis
Scan-based BIST fault diagnosis
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Scan-based BIST fault diagnosis

Yuejian Wu ; Adham, S.M.I.

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-02, Vol.18 (2), p.203-211 [Periódico revisado por pares]

New York, NY: IEEE

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5
A low overhead design for testability and test generation technique for core-based systems-on-a-chip
A low overhead design for testability and test generation technique for core-based systems-on-a-chip
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A low overhead design for testability and test generation technique for core-based systems-on-a-chip

Ghosh, I. ; Jha, N.K. ; Dey, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 1999, Vol.18 (11), p.1661-1676 [Periódico revisado por pares]

IEEE

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6
COMPACTEST: a method to generate compact test sets for combinational circuits
COMPACTEST: a method to generate compact test sets for combinational circuits
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COMPACTEST: a method to generate compact test sets for combinational circuits

Pomeranz, I. ; Reddy, L.N. ; Reddy, S.M.

IEEE transactions on computer-aided design of integrated circuits and systems, 1993-07, Vol.12 (7), p.1040-1049 [Periódico revisado por pares]

New York, NY: IEEE

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7
Optimal State Assignment for Finite State Machines
Optimal State Assignment for Finite State Machines
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Optimal State Assignment for Finite State Machines

De Micheli, G. ; Brayton, R.K. ; Sangiovanni-Vincentelli, A.

IEEE transactions on computer-aided design of integrated circuits and systems, 1985-01, Vol.4 (3), p.269-285 [Periódico revisado por pares]

New York, NY: IEEE

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8
Design automation tools for efficient implementation of logic functions by decomposition
Design automation tools for efficient implementation of logic functions by decomposition
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Design automation tools for efficient implementation of logic functions by decomposition

Varma, D. ; Trachtenberg, E.A.

IEEE transactions on computer-aided design of integrated circuits and systems, 1989-08, Vol.8 (8), p.901-916 [Periódico revisado por pares]

New York, NY: IEEE

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9
A New Design-Centering Methodology for VLSI Device Development
A New Design-Centering Methodology for VLSI Device Development
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A New Design-Centering Methodology for VLSI Device Development

Aoki, Y. ; Masuda, H. ; Shimada, S. ; Sato, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 1987-05, Vol.6 (3), p.452-461 [Periódico revisado por pares]

New York, NY: IEEE

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10
CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design
CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design
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CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design

Ueda, K. ; Kitazawa, H. ; Harada, I.

IEEE transactions on computer-aided design of integrated circuits and systems, 1985-01, Vol.4 (1), p.12-22 [Periódico revisado por pares]

New York, NY: IEEE

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