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Ambient assisted living spaces validation by services and devices simulation
Ambient assisted living spaces validation by services and devices simulation
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Ambient assisted living spaces validation by services and devices simulation

Fernandez-Llatas, C. ; Mocholi, J. B. ; Sala, P. ; Naranjo, J. C. ; Pileggi, S. F. ; Guillen, S. ; Traver, V.

2011 Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011, p.1785-1788

IEEE

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Multimode WSN: Improving Robustness, Fault Tolerance and Performance of Randomly Deployed Wireless Sensor Network
Multimode WSN: Improving Robustness, Fault Tolerance and Performance of Randomly Deployed Wireless Sensor Network
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Multimode WSN: Improving Robustness, Fault Tolerance and Performance of Randomly Deployed Wireless Sensor Network

Pileggi, S F ; Palau, C E ; Esteve, M

2010 2nd International Conference on Computational Intelligence, Communication Systems and Networks, 2010, p.112-117

IEEE

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3
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
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Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction

Li, Peng ; Liu, Frank ; Li, Xin ; Pileggi, Lawrence T. ; Nassif, Sani R.

Design, Automation and Test in Europe, 2005, p.958-963

Washington, DC, USA: IEEE Computer Society

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4
Polar format synthetic aperture radar in energy efficient application-specific logic-in-memory
Polar format synthetic aperture radar in energy efficient application-specific logic-in-memory
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Polar format synthetic aperture radar in energy efficient application-specific logic-in-memory

Qiuling Zhu ; Berger, C. R. ; Turner, E. L. ; Pileggi, L. ; Franchetti, F.

2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2012, p.1557-1560

IEEE

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5
CMOS gate delay models for general RLC loading
CMOS gate delay models for general RLC loading
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CMOS gate delay models for general RLC loading

Arunachalam, R. ; Dartu, F. ; Pileggi, L.T.

Proceedings International Conference on Computer Design VLSI in Computers and Processors, 1997, p.224-229

IEEE

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6
An explicit RC-circuit delay approximation based on the first three moments of the impulse response
An explicit RC-circuit delay approximation based on the first three moments of the impulse response
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An explicit RC-circuit delay approximation based on the first three moments of the impulse response

Tutuianu, B. ; Dartu, F. ; Pileggi, L.

33rd Design Automation Conference Proceedings, 1996, 1996, p.611-616

IEEE

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7
TETA: transistor-level engine for timing analysis
TETA: transistor-level engine for timing analysis
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TETA: transistor-level engine for timing analysis

Dartu, Florentin ; Pileggi, Lawrence T. Irwin, M. J.

Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.595-598

New York, NY, USA: ACM

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8
RC-interconnect macromodels for timing simulation
RC-interconnect macromodels for timing simulation
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RC-interconnect macromodels for timing simulation

Dartu, F. ; Tutuianu, B. ; Pileggi, L.T.

33rd Design Automation Conference Proceedings, 1996, 1996, p.544-547

IEEE

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9
Clustering and load balancing for buffered clock tree synthesis
Clustering and load balancing for buffered clock tree synthesis
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Clustering and load balancing for buffered clock tree synthesis

Mehta, A.D. ; Yao-Ping Chen ; Menezes, N. ; Wong, D.F. ; Pilegg, L.T.

Proceedings International Conference on Computer Design VLSI in Computers and Processors, 1997, p.217-223

IEEE

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