Result Number | Material Type | Add to My Shelf Action | Record Details and Options |
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1 |
Material Type: Artigo
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TETA: transistor-level waveform evaluation for timing analysisAcar, E. ; Dartu, F. ; Pileggi, L.T.IEEE transactions on computer-aided design of integrated circuits and systems, 2002-05, Vol.21 (5), p.605-616 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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2 |
Material Type: Ata de Congresso
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Modeling Interconnect Variability Using Efficient Parametric Model Order ReductionLi, Peng ; Liu, Frank ; Li, Xin ; Pileggi, Lawrence T. ; Nassif, Sani R.Design, Automation and Test in Europe, 2005, p.958-963Washington, DC, USA: IEEE Computer SocietyTexto completo disponível |
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3 |
Material Type: Artigo
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Performance computation for precharacterized CMOS gates with RC loadsDartu, F. ; Menezes, N. ; Pileggi, L.T.IEEE transactions on computer-aided design of integrated circuits and systems, 1996-05, Vol.15 (5), p.544-553 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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4 |
Material Type: Ata de Congresso
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An explicit RC-circuit delay approximation based on the first three moments of the impulse responseTutuianu, B. ; Dartu, F. ; Pileggi, L.33rd Design Automation Conference Proceedings, 1996, 1996, p.611-616IEEETexto completo disponível |
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5 |
Material Type: Ata de Congresso
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TETA: transistor-level engine for timing analysisDartu, Florentin ; Pileggi, Lawrence T. Irwin, M. J.Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.595-598New York, NY, USA: ACMTexto completo disponível |
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6 |
Material Type: Ata de Congresso
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RC-interconnect macromodels for timing simulationDartu, F. ; Tutuianu, B. ; Pileggi, L.T.33rd Design Automation Conference Proceedings, 1996, 1996, p.544-547IEEETexto completo disponível |