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Prime-Factor GFFT Architecture for Fast Frequency Domain Decoding of Cyclic Codes
Prime-Factor GFFT Architecture for Fast Frequency Domain Decoding of Cyclic Codes
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Prime-Factor GFFT Architecture for Fast Frequency Domain Decoding of Cyclic Codes

CHANG, Yanyan ; ZHANG, Wei ; WANG, Hao ; SHI, Lina ; LIU, Yanyan

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2024/01/01, Vol.E107.A(1), pp.174-177 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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2
Vehicle Re-Identification Based on Quadratic Split Architecture and Auxiliary Information Embedding
Vehicle Re-Identification Based on Quadratic Split Architecture and Auxiliary Information Embedding
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Vehicle Re-Identification Based on Quadratic Split Architecture and Auxiliary Information Embedding

LU, Tongwei ; ZHANG, Hao ; MIN, Feng ; JIA, Shihai

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2022/12/01, Vol.E105.A(12), pp.1621-1625 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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3
High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA
High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA
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High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA

RANAWAKA, Piyumal ; EKPANYAPONG, Mongkol ; TAVARES, Adriano ; DAILEY, Mathew ; ATHIKULWONGSE, Krit ; SILVA, Vitor

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2019/12/01, Vol.E102.A(12), pp.1792-1803 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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4
Simultaneous Scheduling and Core-Type Optimization for Moldable Fork-Join Tasks on Heterogeneous Multicores
Simultaneous Scheduling and Core-Type Optimization for Moldable Fork-Join Tasks on Heterogeneous Multicores
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Simultaneous Scheduling and Core-Type Optimization for Moldable Fork-Join Tasks on Heterogeneous Multicores

NISHIKAWA, Hiroki ; SHIMADA, Kana ; TANIGUCHI, Ittetsu ; TOMIYAMA, Hiroyuki

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2022/03/01, Vol.E105.A(3), pp.540-548 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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5
Adaptive Channel Scheduling for Acceleration and Fine Control of RNN-Based Image Compression
Adaptive Channel Scheduling for Acceleration and Fine Control of RNN-Based Image Compression
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Adaptive Channel Scheduling for Acceleration and Fine Control of RNN-Based Image Compression

KIM, Sang Hoon ; KO, Jong Hwan

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2023/09/01, Vol.E106.A(9), pp.1211-1215 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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6
Convergence Acceleration via Chebyshev Step: Plausible Interpretation of Deep-Unfolded Gradient Descent
Convergence Acceleration via Chebyshev Step: Plausible Interpretation of Deep-Unfolded Gradient Descent
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Convergence Acceleration via Chebyshev Step: Plausible Interpretation of Deep-Unfolded Gradient Descent

TAKABE, Satoshi ; WADAYAMA, Tadashi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2022/08/01, Vol.E105.A(8), pp.1110-1120 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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7
Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework
Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework
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Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework

YOSHIYA, Eiji ; NAKANISHI, Tomoya ; ISSHIKI, Tsuyoshi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2022/07/01, Vol.E105.A(7), pp.1061-1069 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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8
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation
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Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation

HATTORI, Naoki ; SHIOMI, Jun ; MASUDA, Yutaka ; ISHIHARA, Tohru ; SHINYA, Akihiko ; NOTOMI, Masaya

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2021/11/01, Vol.E104.A(11), pp.1477-1487 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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9
Scalable and Parameterized Architecture for Efficient Stream Mining
Scalable and Parameterized Architecture for Efficient Stream Mining
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Scalable and Parameterized Architecture for Efficient Stream Mining

ZHANG, Li ; LI, Dawei ; ZOU, Xuecheng ; HU, Yu ; XU, Xiaowei

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2018/01/01, Vol.E101.A(1), pp.219-231 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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10
Power Analysis on Unrolled Architecture with Points-of-Interest Search and Its Application to PRINCE Block Cipher
Power Analysis on Unrolled Architecture with Points-of-Interest Search and Its Application to PRINCE Block Cipher
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Power Analysis on Unrolled Architecture with Points-of-Interest Search and Its Application to PRINCE Block Cipher

Yli-Maeyry, Ville ; Homma, Naofumi ; Aoki, Takafumi

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2017-01, Vol.E100.A (1), p.149-157 [Periódico revisado por pares]

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