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Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints
Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints
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Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints

Chabini, N. ; Wolf, W.

IEEE transactions on very large scale integration (VLSI) systems, 2005-10, Vol.13 (10), p.1113-1126 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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2
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling
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Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling

Chabini, N. ; Wolf, W.

IEEE transactions on very large scale integration (VLSI) systems, 2004-06, Vol.12 (6), p.573-589 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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3
A linear inverse space-mapping (LISM) algorithm to design linear and nonlinear RF and microwave circuits
A linear inverse space-mapping (LISM) algorithm to design linear and nonlinear RF and microwave circuits
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A linear inverse space-mapping (LISM) algorithm to design linear and nonlinear RF and microwave circuits

Rayas-Sanchez, J.E. ; Lara-Rojo, F. ; Martinez-Guerrero, E.

IEEE transactions on microwave theory and techniques, 2005-03, Vol.53 (3), p.960-968 [Periódico revisado por pares]

New York, NY: IEEE

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4
Overlap-Save and Overlap-Add Filters: Optimal Design and Comparison
Overlap-Save and Overlap-Add Filters: Optimal Design and Comparison
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Overlap-Save and Overlap-Add Filters: Optimal Design and Comparison

Daher, Ali ; Baghious, El-Houssain ; Burel, Gilles ; Radoi, Emanuel

IEEE transactions on signal processing, 2010-06, Vol.58 (6), p.3066-3075 [Periódico revisado por pares]

New York, NY: IEEE

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5
Linear matrix inequality formulation of spectral mask constraints with applications to FIR filter design
Linear matrix inequality formulation of spectral mask constraints with applications to FIR filter design
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Linear matrix inequality formulation of spectral mask constraints with applications to FIR filter design

Davidson, T.N. ; Zhi-Quan Luo ; Sturm, J.F.

IEEE transactions on signal processing, 2002-11, Vol.50 (11), p.2702-2715 [Periódico revisado por pares]

New York, NY: IEEE

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6
On the Design of Highly Accurate and Efficient IIR and FIR Filters
On the Design of Highly Accurate and Efficient IIR and FIR Filters
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On the Design of Highly Accurate and Efficient IIR and FIR Filters

Beylkin, Gregory ; Lewis, Ryan D. ; Monzón, Lucas

IEEE transactions on signal processing, 2012-08, Vol.60 (8), p.4045-4054 [Periódico revisado por pares]

New York, NY: IEEE

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7
Seeker Optimization Algorithm for Digital IIR Filter Design
Seeker Optimization Algorithm for Digital IIR Filter Design
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Seeker Optimization Algorithm for Digital IIR Filter Design

Dai, Chaohua ; Chen, Weirong ; Zhu, Yunfang

IEEE transactions on industrial electronics (1982), 2010-05, Vol.57 (5), p.1710-1718 [Periódico revisado por pares]

New York: IEEE

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8
Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware
Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware
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Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware

Shan, Weiwei ; Chen, Xin ; Li, Bo ; Cao, Peng ; Li, Jie ; Gao, Gugang ; Shi, Longxing

IEEE transactions on instrumentation and measurement, 2013-10, Vol.62 (10), p.2716-2724 [Periódico revisado por pares]

IEEE

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9
Partitioning and pipelining for performance-constrained hardware/software systems
Partitioning and pipelining for performance-constrained hardware/software systems
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Partitioning and pipelining for performance-constrained hardware/software systems

Bakshi, S. ; Gajski, D.D.

IEEE transactions on very large scale integration (VLSI) systems, 1999-12, Vol.7 (4), p.419-432 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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10
Efficient timing closure without timing driven placement and routing
Efficient timing closure without timing driven placement and routing
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Efficient timing closure without timing driven placement and routing

Vujkovic, Miodrag ; Wadkins, David ; Swartz, Bill ; Sechen, Carl

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.268-273

Piscataway NJ: ACM

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