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Material Type: Ata de Congresso
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Legalization algorithm for multiple-row height standard cell designWing-Kai Chow ; Chak-Wa Pui ; Young, Evangeline F. Y.2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6IEEESem texto completo |
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Material Type: Ata de Congresso
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Flip-flop clustering by weighted K-means algorithmGang Wu ; Yue Xu ; Dean Wu ; Ragupathy, Manoj ; Yu-yen Mo ; Chu, Chris2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6IEEESem texto completo |
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Material Type: Ata de Congresso
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Incremental layer assignment for critical path timingDerong Liu ; Bei Yu ; Chowdhury, Salim ; Pan, David Z.2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6IEEESem texto completo |
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Material Type: Ata de Congresso
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DAG-aware logic synthesis of datapathsCunxi Yu ; Ciesielski, Maciej ; Choudhury, Mihir ; Sullivan, Andrew2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6IEEESem texto completo |
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Material Type: Artigo
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MITA: Multi-Input Adaptive Activation Function for Accurate Binary Neural Network HardwareZHANG, Peiqi ; TAKAMAEDA-YAMAZAKI, ShinyaIEICE Transactions on Information and Systems, 2023/12/01, Vol.E106.D(12), pp.2006-2014 [Periódico revisado por pares]Tokyo: The Institute of Electronics, Information and Communication EngineersTexto completo disponível |
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Material Type: Artigo
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Design and FPGA-Based Realization of a Chaotic Secure Video Communication SystemChen, Shikun ; Yu, Simin ; Lu, Jinhu ; Chen, Guanrong ; He, JianbinIEEE transactions on circuits and systems for video technology, 2018-09, Vol.28 (9), p.2359-2371 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Adaptive Subsampling for ROI-Based Visual Tracking: Algorithms and FPGA ImplementationIqbal, Odrika ; Muro, Victor Isaac Torres ; Katoch, Sameeksha ; Spanias, Andreas ; Jayasuriya, SurenIEEE access, 2022, Vol.10, p.90507-90522 [Periódico revisado por pares]Piscataway: IEEETexto completo disponível |
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Material Type: Artigo
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Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and ImplementationMu, Jianan ; Ren, Yi ; Wang, Wen ; Hu, Yizhong ; Chen, Shuai ; Chang, Chip-Hong ; Fan, Junfeng ; Ye, Jing ; Cao, Yuan ; Li, Huawei ; Li, XiaoweiIEEE transactions on computer-aided design of integrated circuits and systems, 2023-05, Vol.42 (5), p.1504-1517 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Ata de Congresso
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V-GR: 3D Global Routing with via Minimization and Multi-Strategy Rip-Up and ReroutingZhang, Ping ; Yao, Pengju ; Li, Xingquan ; Yu, Bei ; Zhu, Wenxing2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 2024, p.963-968Piscataway, NJ, USA: IEEE PressSem texto completo |
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Material Type: Artigo
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FPGA Implementation of the Fractional Order Integrator/Differentiator: Two Approaches and ApplicationsTolba, Mohammed F. ; Said, Lobna A. ; Madian, Ahmed H. ; Radwan, Ahmed G.IEEE transactions on circuits and systems. I, Regular papers, 2019-04, Vol.66 (4), p.1484-1495 [Periódico revisado por pares]New York: IEEETexto completo disponível |