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Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems
| Result Number | Material Type | Add to My Shelf Action | Record Details and Options |
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SASCHA -Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network AccelerationRomaszkan, Wojciech ; Li, Tianmu ; Gupta, PuneetIEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.1-1 [Peer Reviewed Journal]New York: IEEEFull text available |
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Hardware/Software Co-Exploration of Neural ArchitecturesJiang, Weiwen ; Yang, Lei ; Sha, Edwin Hsing-Mean ; Zhuge, Qingfeng ; Gu, Shouzhen ; Dasgupta, Sakyasingha ; Shi, Yiyu ; Hu, JingtongIEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4805-4815 [Peer Reviewed Journal]IEEEFull text available |
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YodaNN: An Architecture for Ultralow Power Binary-Weight CNN AccelerationAndri, Renzo ; Cavigelli, Lukas ; Rossi, Davide ; Benini, LucaIEEE transactions on computer-aided design of integrated circuits and systems, 2018-01, Vol.37 (1), p.48-60 [Peer Reviewed Journal]IEEEFull text available |
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RANC: Reconfigurable Architecture for Neuromorphic ComputingMack, Joshua ; Purdy, Ruben ; Rockowitz, Kris ; Inouye, Michael ; Richter, Edward ; Valancius, Spencer ; Kumbhare, Nirmal ; Hassan, Md Sahil ; Fair, Kaitlin ; Mixter, John ; Akoglu, AliIEEE transactions on computer-aided design of integrated circuits and systems, 2021-11, Vol.40 (11), p.2265-2278 [Peer Reviewed Journal]New York: IEEEFull text available |
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ASSURED: Architecture for Secure Software Update of Realistic Embedded DevicesAsokan, N. ; Nyman, Thomas ; Rattanavipanon, Norrathep ; Sadeghi, Ahmad-Reza ; Tsudik, GeneIEEE transactions on computer-aided design of integrated circuits and systems, 2018-11, Vol.37 (11), p.2290-2300 [Peer Reviewed Journal]New York: IEEEFull text available |
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Rubik: A Hierarchical Architecture for Efficient Graph Neural Network TrainingChen, Xiaobing ; Wang, Yuke ; Xie, Xinfeng ; Hu, Xing ; Basak, Abanti ; Liang, Ling ; Yan, Mingyu ; Deng, Lei ; Ding, Yufei ; Du, Zidong ; Xie, YuanIEEE transactions on computer-aided design of integrated circuits and systems, 2022-04, Vol.41 (4), p.936-949 [Peer Reviewed Journal]New York: IEEEFull text available |
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Architecture Considerations for Stochastic Computing AcceleratorsLee, Vincent T. ; Alaghi, Armin ; Pamula, Rajesh ; Sathe, Visvesh S. ; Ceze, Luis ; Oskin, MarkIEEE transactions on computer-aided design of integrated circuits and systems, 2018-11, Vol.37 (11), p.2277-2289 [Peer Reviewed Journal]New York: IEEEFull text available |
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Morphling: A Reconfigurable Architecture for Tensor ComputationLu, Liqiang ; Liang, YunIEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.4733-4746 [Peer Reviewed Journal]New York: IEEEFull text available |
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M²NAS: Joint Neural Architecture Optimization System With Network TransmissionWang, Lanfei ; Xie, Lingxi ; Bi, Kaifeng ; Zhao, Kaili ; Guo, Jun ; Tian, QiIEEE transactions on computer-aided design of integrated circuits and systems, 2023-08, Vol.42 (8), p.2631-2642 [Peer Reviewed Journal]New York: IEEEFull text available |
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LightNAS: On Lightweight and Scalable Neural Architecture Search for Embedded PlatformsLuo, Xiangzhong ; Liu, Di ; Kong, Hao ; Huai, Shuo ; Chen, Hui ; Liu, WeichenIEEE transactions on computer-aided design of integrated circuits and systems, 2023-06, Vol.42 (6), p.1784-1797 [Peer Reviewed Journal]New York: IEEEFull text available |
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