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Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
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Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

Ma, Yufei ; Cao, Yu ; Vrudhula, Sarma ; Seo, Jae-sun

IEEE transactions on very large scale integration (VLSI) systems, 2018-07, Vol.26 (7), p.1354-1367 [Periódico revisado por pares]

New York: IEEE

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2
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
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High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Ueno, Rei ; Homma, Naofumi ; Morioka, Sumio ; Miura, Noriyuki ; Matsuda, Kohei ; Nagata, Makoto ; Bhasin, Shivam ; Mathieu, Yves ; Graba, Tarik ; Danger, Jean-Luc

IEEE transactions on computers, 2020-04, Vol.69 (4), p.534-548 [Periódico revisado por pares]

New York: IEEE

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3
Partially-Connected Neural Architecture Search for Reduced Computational Redundancy
Partially-Connected Neural Architecture Search for Reduced Computational Redundancy
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Partially-Connected Neural Architecture Search for Reduced Computational Redundancy

Xu, Yuhui ; Xie, Lingxi ; Dai, Wenrui ; Zhang, Xiaopeng ; Chen, Xin ; Qi, Guo-Jun ; Xiong, Hongkai ; Tian, Qi

IEEE transactions on pattern analysis and machine intelligence, 2021-09, Vol.43 (9), p.2953-2970 [Periódico revisado por pares]

United States: IEEE

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4
A Survey on Evolutionary Neural Architecture Search
A Survey on Evolutionary Neural Architecture Search
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A Survey on Evolutionary Neural Architecture Search

Liu, Yuqiao ; Sun, Yanan ; Xue, Bing ; Zhang, Mengjie ; Yen, Gary G. ; Tan, Kay Chen

IEEE transaction on neural networks and learning systems, 2023-02, Vol.34 (2), p.550-570

United States: IEEE

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5
Completely Automated CNN Architecture Design Based on Blocks
Completely Automated CNN Architecture Design Based on Blocks
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Completely Automated CNN Architecture Design Based on Blocks

Sun, Yanan ; Xue, Bing ; Zhang, Mengjie ; Yen, Gary G.

IEEE transaction on neural networks and learning systems, 2020-04, Vol.31 (4), p.1242-1254

United States: IEEE

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6
Software Architecture Optimization Methods: A Systematic Literature Review
Software Architecture Optimization Methods: A Systematic Literature Review
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Software Architecture Optimization Methods: A Systematic Literature Review

Aleti, A. ; Buhnova, B. ; Grunske, L. ; Koziolek, A. ; Meedeniya, I.

IEEE transactions on software engineering, 2013-05, Vol.39 (5), p.658-683 [Periódico revisado por pares]

New York: IEEE

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7
Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture
Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture
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Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture

Sun, Hanbo ; Zhu, Zhenhua ; Wang, Chenyu ; Ning, Xuefei ; Dai, Guohao ; Yang, Huazhong ; Wang, Yu

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1 [Periódico revisado por pares]

New York: IEEE

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8
Towards Accurate and Compact Architectures via Neural Architecture Transformer
Towards Accurate and Compact Architectures via Neural Architecture Transformer
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Towards Accurate and Compact Architectures via Neural Architecture Transformer

Guo, Yong ; Zheng, Yin ; Tan, Mingkui ; Chen, Qi ; Li, Zhipeng ; Chen, Jian ; Zhao, Peilin ; Huang, Junzhou

IEEE transactions on pattern analysis and machine intelligence, 2022-10, Vol.44 (10), p.6501-6516 [Periódico revisado por pares]

United States: IEEE

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9
An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures
An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures
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An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures

Zulehner, Alwin ; Paler, Alexandru ; Wille, Robert

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-07, Vol.38 (7), p.1226-1236 [Periódico revisado por pares]

New York: IEEE

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10
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
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Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators

Jiang, Weiwen ; Lou, Qiuwen ; Yan, Zheyu ; Yang, Lei ; Hu, Jingtong ; Hu, Xiaobo Sharon ; Shi, Yiyu

IEEE transactions on computers, 2021-04, Vol.70 (4), p.595-605 [Periódico revisado por pares]

IEEE

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