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First record of the spatial organization of the nucleosome‐less chromatin of dinoflagellates: The nonrandom distribution of microsatellites and bipolar arrangement of telomeres in the nucleus of Gambierdiscus australes (Dinophyceae)
First record of the spatial organization of the nucleosome‐less chromatin of dinoflagellates: The nonrandom distribution of microsatellites and bipolar arrangement of telomeres in the nucleus of Gambierdiscus australes (Dinophyceae)
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First record of the spatial organization of the nucleosome‐less chromatin of dinoflagellates: The nonrandom distribution of microsatellites and bipolar arrangement of telomeres in the nucleus of Gambierdiscus australes (Dinophyceae)

Cuadrado, Ángeles ; Figueroa, Rosa I. ; Sixto, Marta ; Bravo, Isabel ; De Bustos, Alfredo ; Lin, S. Lin, S.

Journal of phycology, 2022-04, Vol.58 (2), p.297-307 [Periódico revisado por pares]

United States: Wiley Subscription Services, Inc

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2
A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation
A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation
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A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation

Arsovski, I. ; Hebig, T. ; Dobson, D. ; Wistort, R.

IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.932-939 [Periódico revisado por pares]

New York, NY: IEEE

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3
Modeling of HCD Kinetics Under Full VG-VD Space, Different Experimental Conditions and Across Different Device Architectures
Modeling of HCD Kinetics Under Full VG-VD Space, Different Experimental Conditions and Across Different Device Architectures
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Modeling of HCD Kinetics Under Full VG-VD Space, Different Experimental Conditions and Across Different Device Architectures

Sharma, Uma ; Mahapatra, Souvik

IEEE journal of the Electron Devices Society, 2020-01, Vol.8, p.1-1 [Periódico revisado por pares]

New York: IEEE

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4
High-Reliability Dynamic-Threshold Source-Side Injection for 2-Bit/Cell With MLC Operation of Wrapped Select-Gate SONOS in nor-Type Flash Memory
High-Reliability Dynamic-Threshold Source-Side Injection for 2-Bit/Cell With MLC Operation of Wrapped Select-Gate SONOS in nor-Type Flash Memory
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High-Reliability Dynamic-Threshold Source-Side Injection for 2-Bit/Cell With MLC Operation of Wrapped Select-Gate SONOS in nor-Type Flash Memory

Wang, Kuan-Ti ; Chao, Tien-Sheng ; Wu, Woei-Cherng ; Yang, Wen-Luh ; Lee, Chien-Hsing ; Hsieh, Tsung-Min ; Liou, Jhyy-Cheng ; Wang, Shen-De ; Chen, Tzu-Ping ; Chen, Chien-Hung ; Lin, Chih-Hung ; Chen, Hwi-Huang

IEEE transactions on electron devices, 2010-09, Vol.57 (9), p.2335-2338 [Periódico revisado por pares]

New York: IEEE

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5
A strategy to emulate NOR flash with NAND flash
A strategy to emulate NOR flash with NAND flash
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A strategy to emulate NOR flash with NAND flash

Chang, Yuan-Hao ; Lin, Jian-Hong ; Hsieh, Jen-Wei ; Kuo, Tei-Wei

ACM transactions on storage, 2010-07, Vol.6 (2), p.1-23 [Periódico revisado por pares]

ACM

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6
A novel self-aligned highly reliable sidewall split-gate flash memory
A novel self-aligned highly reliable sidewall split-gate flash memory
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A novel self-aligned highly reliable sidewall split-gate flash memory

Caleb Yu-Sheng Cho ; Ming-Jer Chen ; Chiou-Feng Chen ; Tuntasood, P. ; Fan, D.-T. ; Tseng-Yi Liu

IEEE transactions on electron devices, 2006-03, Vol.53 (3), p.465-473 [Periódico revisado por pares]

New York, NY: IEEE

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7
Design of monostable–bistable transition logic element using the BiCMOS-based negative differential resistance circuit
Design of monostable–bistable transition logic element using the BiCMOS-based negative differential resistance circuit
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Design of monostable–bistable transition logic element using the BiCMOS-based negative differential resistance circuit

Gan, Kwang-Jow ; Tsai, Cher-Shiung ; Hsien, Chi-Wen ; Li, Yu-Kuang ; Yeh, Wen-Kuan

Analog integrated circuits and signal processing, 2011-09, Vol.68 (3), p.379-385 [Periódico revisado por pares]

Boston: Springer US

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8
Combinational Logic Design (Part I)
Combinational Logic Design (Part I)
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Combinational Logic Design (Part I)

Taraate, Vaibbhav

Digital Logic Design Using Verilog, 2016, p.27-52

India: Springer (India) Private Limited

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9
A NOR Emulation Strategy over NAND Flash Memory
A NOR Emulation Strategy over NAND Flash Memory
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A NOR Emulation Strategy over NAND Flash Memory

Jian-Hong Lin ; Yuan-Hao Chang ; Jen-Wei Hsieh ; Tei-Wei Kuo ; Cheng-Chih Yang

13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007, p.95-102

IEEE

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