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Refinado por: Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover
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21
Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review
Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review
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Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review

Hassan, Ahmad ; Savaria, Yvon ; Sawan, Mohamad

IEEE transactions on very large scale integration (VLSI) systems, 2018-10, Vol.26 (10), p.2085-2098 [Periódico revisado por pares]

New York: IEEE

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22
High-Performance Concatenation Decoding of Reed-Solomon Codes With SPC Codes
High-Performance Concatenation Decoding of Reed-Solomon Codes With SPC Codes
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High-Performance Concatenation Decoding of Reed-Solomon Codes With SPC Codes

Gao, Jiajing ; Zhang, Wei ; Liu, Yanyan ; Wang, Hao ; Zhao, Jianhan

IEEE transactions on very large scale integration (VLSI) systems, 2021-09, Vol.29 (9), p.1670-1674 [Periódico revisado por pares]

IEEE

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23
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
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Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications

Giterman, Robert ; Atias, Lior ; Teman, Adam

IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.502-509 [Periódico revisado por pares]

New York: IEEE

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24
Efficient Architectures for Multigigabit CCSDS LDPC Encoders
Efficient Architectures for Multigigabit CCSDS LDPC Encoders
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Efficient Architectures for Multigigabit CCSDS LDPC Encoders

Theodoropoulos, Dimitris ; Kranitis, Nektarios ; Tsigkanos, Antonis ; Paschalis, Antonios

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1118-1127 [Periódico revisado por pares]

New York: IEEE

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25
A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement
A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement
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A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement

Park, Jin Woo ; Lee, Hyokeun ; Kim, Boyeal ; Kang, Dong-Goo ; Jin, Seung Oh ; Kim, Hyun ; Lee, Hyuk-Jae

IEEE transactions on very large scale integration (VLSI) systems, 2020-01, Vol.28 (1), p.101-114 [Periódico revisado por pares]

New York: IEEE

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26
High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1
High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1
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High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1

Tsigkanos, Antonis ; Kranitis, Nektarios ; Theodoropoulos, Dimitris ; Paschalis, Antonios

IEEE transactions on very large scale integration (VLSI) systems, 2020-11, Vol.28 (11), p.2397-2409 [Periódico revisado por pares]

New York: IEEE

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27
Efficient Error Estimation for High-Level Design Space Exploration of Approximate Computing Systems
Efficient Error Estimation for High-Level Design Space Exploration of Approximate Computing Systems
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Efficient Error Estimation for High-Level Design Space Exploration of Approximate Computing Systems

Vaeztourshizi, Marzieh ; Pedram, Massoud

IEEE transactions on very large scale integration (VLSI) systems, 2023-07, Vol.31 (7), p.1-14 [Periódico revisado por pares]

New York: IEEE

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28
EGRA: A Coarse Grained Reconfigurable Architectural Template
EGRA: A Coarse Grained Reconfigurable Architectural Template
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EGRA: A Coarse Grained Reconfigurable Architectural Template

Ansaloni, Giovanni ; Bonzini, Paolo ; Pozzi, Laura

IEEE transactions on very large scale integration (VLSI) systems, 2011-06, Vol.19 (6), p.1062-1074 [Periódico revisado por pares]

New York, NY: IEEE

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29
Toward Self-Tunable Approximate Computing
Toward Self-Tunable Approximate Computing
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Toward Self-Tunable Approximate Computing

Xu, Siyuan ; Schafer, Benjamin Carrion

IEEE transactions on very large scale integration (VLSI) systems, 2019-04, Vol.27 (4), p.778-789 [Periódico revisado por pares]

New York: IEEE

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30
Design Space Exploration for Chiplet-Assembly-Based Processors
Design Space Exploration for Chiplet-Assembly-Based Processors
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Design Space Exploration for Chiplet-Assembly-Based Processors

Pal, Saptadeep ; Petrisko, Daniel ; Kumar, Rakesh ; Gupta, Puneet

IEEE transactions on very large scale integration (VLSI) systems, 2020-04, Vol.28 (4), p.1062-1073 [Periódico revisado por pares]

New York: IEEE

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