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Refinado por: Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover assunto: Software remover
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ORION 2.0: A Power-Area Simulator for Interconnection Networks
ORION 2.0: A Power-Area Simulator for Interconnection Networks
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ORION 2.0: A Power-Area Simulator for Interconnection Networks

Kahng, A. B. ; Bin Li ; Li-Shiuan Peh ; Samadi, K.

IEEE transactions on very large scale integration (VLSI) systems, 2012-01, Vol.20 (1), p.191-196 [Periódico revisado por pares]

New York, NY: IEEE

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2
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications
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Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications

Zhao, Qiang ; Peng, Chunyu ; Chen, Junning ; Lin, Zhiting ; Wu, Xiulong

IEEE transactions on very large scale integration (VLSI) systems, 2020-03, Vol.28 (3), p.848-852 [Periódico revisado por pares]

New York: IEEE

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3
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators
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ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators

Putra, Rachmad Vidya Wicaksana ; Hanif, Muhammad Abdullah ; Shafique, Muhammad

IEEE transactions on very large scale integration (VLSI) systems, 2021-04, Vol.29 (4), p.702-715 [Periódico revisado por pares]

New York: IEEE

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4
Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level
Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level
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Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level

Siyuan Xu ; Schafer, Benjamin Carrion

IEEE transactions on very large scale integration (VLSI) systems, 2017-11, Vol.25 (11), p.3077-3088 [Periódico revisado por pares]

IEEE

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5
"It's a small world after all": NoC performance optimization via long-range link insertion
"It's a small world after all": NoC performance optimization via long-range link insertion
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"It's a small world after all": NoC performance optimization via long-range link insertion

Ogras, U.Y. ; Marculescu, R.

IEEE transactions on very large scale integration (VLSI) systems, 2006-07, Vol.14 (7), p.693-706 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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6
Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review
Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review
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Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review

Hassan, Ahmad ; Savaria, Yvon ; Sawan, Mohamad

IEEE transactions on very large scale integration (VLSI) systems, 2018-10, Vol.26 (10), p.2085-2098 [Periódico revisado por pares]

New York: IEEE

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7
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
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Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications

Giterman, Robert ; Atias, Lior ; Teman, Adam

IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.502-509 [Periódico revisado por pares]

New York: IEEE

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8
A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement
A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement
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A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement

Park, Jin Woo ; Lee, Hyokeun ; Kim, Boyeal ; Kang, Dong-Goo ; Jin, Seung Oh ; Kim, Hyun ; Lee, Hyuk-Jae

IEEE transactions on very large scale integration (VLSI) systems, 2020-01, Vol.28 (1), p.101-114 [Periódico revisado por pares]

New York: IEEE

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9
EGRA: A Coarse Grained Reconfigurable Architectural Template
EGRA: A Coarse Grained Reconfigurable Architectural Template
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EGRA: A Coarse Grained Reconfigurable Architectural Template

Ansaloni, Giovanni ; Bonzini, Paolo ; Pozzi, Laura

IEEE transactions on very large scale integration (VLSI) systems, 2011-06, Vol.19 (6), p.1062-1074 [Periódico revisado por pares]

New York, NY: IEEE

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10
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
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A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors

Karuri, K. ; Chattopadhyay, A. ; Xiaolin Chen ; Kammler, D. ; Ling Hao ; Leupers, R. ; Meyr, H. ; Ascheid, G.

IEEE transactions on very large scale integration (VLSI) systems, 2008-10, Vol.16 (10), p.1281-1294 [Periódico revisado por pares]

New York: IEEE

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