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Refinado por: Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover assunto: Space Exploration remover
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CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration
CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration
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CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration

Sa, Bruno ; Valente, Luca ; Martins, Jose ; Rossi, Davide ; Benini, Luca ; Pinto, Sandro

IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1-14 [Periódico revisado por pares]

New York: IEEE

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BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning
BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning
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BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning

Zheng, Xin ; Cheng, Mingjun ; Chen, Jiasong ; Gao, Huaien ; Xiong, Xiaoming ; Cai, Shuting

IEEE transactions on very large scale integration (VLSI) systems, 2024-05, Vol.32 (5), p.860-869 [Periódico revisado por pares]

New York: IEEE

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3
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization
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HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization

Dai, Yuan ; Li, Jingyuan ; Zhu, Qilong ; Qiu, Yunhui ; Hu, Yihan ; Yin, Wenbo ; Wang, Lingli

IEEE transactions on very large scale integration (VLSI) systems, 2024-03, Vol.32 (3), p.505-518 [Periódico revisado por pares]

New York: IEEE

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4
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning
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Microarchitecture Design Space Exploration via Pareto-Driven Active Learning

Zhai, Jianwang ; Cai, Yici

IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1727-1739 [Periódico revisado por pares]

New York: IEEE

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5
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse
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Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Kim, Jinwoo ; Murali, Gauthaman ; Park, Heechun ; Qin, Eric ; Kwon, Hyoukjun ; Chekuri, Venkata Chaitanya Krishna ; Rahman, Nael Mizanur ; Dasari, Nihar ; Singh, Arvind ; Lee, Minah ; Torun, Hakki Mert ; Roy, Kallol ; Swaminathan, Madhavan ; Mukhopadhyay, Saibal ; Krishna, Tushar ; Lim, Sung Kyu

IEEE transactions on very large scale integration (VLSI) systems, 2020-11, Vol.28 (11), p.2424-2437 [Periódico revisado por pares]

New York: IEEE

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6
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators
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FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators

Marchisio, Alberto ; Mrazek, Vojtech ; Hanif, Muhammad Abdullah ; Shafique, Muhammad

IEEE transactions on very large scale integration (VLSI) systems, 2021-04, Vol.29 (4), p.716-729 [Periódico revisado por pares]

New York: IEEE

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7
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators
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ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators

Putra, Rachmad Vidya Wicaksana ; Hanif, Muhammad Abdullah ; Shafique, Muhammad

IEEE transactions on very large scale integration (VLSI) systems, 2021-04, Vol.29 (4), p.702-715 [Periódico revisado por pares]

New York: IEEE

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8
Synthesis of Approximate Parallel-Prefix Adders
Synthesis of Approximate Parallel-Prefix Adders
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Synthesis of Approximate Parallel-Prefix Adders

Stefanidis, Apostolos ; Zoumpoulidou, Ioanna ; Filippas, Dionysios ; Dimitrakopoulos, Giorgos ; Sirakoulis, Georgios Ch

IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1-14 [Periódico revisado por pares]

New York: IEEE

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9
Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers
Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers
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Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers

Mandal, Sumit K. ; Narayana, Shruti Yadav ; Ayoub, Raid ; Kishinevsky, Michael ; Abousamra, Ahmed ; Ogras, Umit Y.

IEEE transactions on very large scale integration (VLSI) systems, 2023-05, Vol.31 (5), p.670-683 [Periódico revisado por pares]

New York: IEEE

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10
Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review
Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review
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Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review

Hassan, Ahmad ; Savaria, Yvon ; Sawan, Mohamad

IEEE transactions on very large scale integration (VLSI) systems, 2018-10, Vol.26 (10), p.2085-2098 [Periódico revisado por pares]

New York: IEEE

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