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Microarchitecture Design Space Exploration via Pareto-Driven Active Learning
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning
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Microarchitecture Design Space Exploration via Pareto-Driven Active Learning

Zhai, Jianwang ; Cai, Yici

IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1727-1739 [Periódico revisado por pares]

New York: IEEE

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2
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network
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Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network

Chaurasiya, Rohit B. ; Shrestha, Rahul

IEEE transactions on very large scale integration (VLSI) systems, 2022-02, Vol.30 (2), p.166-176 [Periódico revisado por pares]

New York: IEEE

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3
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design
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Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design

Pereira, Pedro Taua Lopes ; Paim, Guilherme ; Costa, Patricia Ucker Leleu da ; Costa, Eduardo Antonio Cesar da ; de Almeida, Sergio Jose Melo ; Bampi, Sergio

IEEE transactions on very large scale integration (VLSI) systems, 2021-07, Vol.29 (7), p.1402-1415 [Periódico revisado por pares]

New York: IEEE

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4
ORION 2.0: A Power-Area Simulator for Interconnection Networks
ORION 2.0: A Power-Area Simulator for Interconnection Networks
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ORION 2.0: A Power-Area Simulator for Interconnection Networks

Kahng, A. B. ; Bin Li ; Li-Shiuan Peh ; Samadi, K.

IEEE transactions on very large scale integration (VLSI) systems, 2012-01, Vol.20 (1), p.191-196 [Periódico revisado por pares]

New York, NY: IEEE

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5
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications
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Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications

Zhao, Qiang ; Peng, Chunyu ; Chen, Junning ; Lin, Zhiting ; Wu, Xiulong

IEEE transactions on very large scale integration (VLSI) systems, 2020-03, Vol.28 (3), p.848-852 [Periódico revisado por pares]

New York: IEEE

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6
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach
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Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach

Pan, Jeng-Shyang ; Lee, Chiou-Yng ; Sghaier, Anissa ; Zeghid, Medien ; Xie, Jiafeng

IEEE transactions on very large scale integration (VLSI) systems, 2019-07, Vol.27 (7), p.1614-1622 [Periódico revisado por pares]

New York: IEEE

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7
Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level
Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level
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Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level

Siyuan Xu ; Schafer, Benjamin Carrion

IEEE transactions on very large scale integration (VLSI) systems, 2017-11, Vol.25 (11), p.3077-3088 [Periódico revisado por pares]

IEEE

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8
Synthesis of Approximate Parallel-Prefix Adders
Synthesis of Approximate Parallel-Prefix Adders
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Synthesis of Approximate Parallel-Prefix Adders

Stefanidis, Apostolos ; Zoumpoulidou, Ioanna ; Filippas, Dionysios ; Dimitrakopoulos, Giorgos ; Sirakoulis, Georgios Ch

IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1-14 [Periódico revisado por pares]

New York: IEEE

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9
Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel
Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel
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Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel

Shadangi, Ashish Ranjan ; Das, Suvra Sekhar ; Chakrabarti, Indrajit

IEEE transactions on very large scale integration (VLSI) systems, 2024-07, Vol.32 (7), p.1285-1296 [Periódico revisado por pares]

New York: IEEE

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10
"It's a small world after all": NoC performance optimization via long-range link insertion
"It's a small world after all": NoC performance optimization via long-range link insertion
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"It's a small world after all": NoC performance optimization via long-range link insertion

Ogras, U.Y. ; Marculescu, R.

IEEE transactions on very large scale integration (VLSI) systems, 2006-07, Vol.14 (7), p.693-706 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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