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Refinado por: Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover
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CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration
CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration
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CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration

Sa, Bruno ; Valente, Luca ; Martins, Jose ; Rossi, Davide ; Benini, Luca ; Pinto, Sandro

IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1-14 [Periódico revisado por pares]

New York: IEEE

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2
BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning
BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning
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BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning

Zheng, Xin ; Cheng, Mingjun ; Chen, Jiasong ; Gao, Huaien ; Xiong, Xiaoming ; Cai, Shuting

IEEE transactions on very large scale integration (VLSI) systems, 2024-05, Vol.32 (5), p.860-869 [Periódico revisado por pares]

New York: IEEE

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3
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning
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Microarchitecture Design Space Exploration via Pareto-Driven Active Learning

Zhai, Jianwang ; Cai, Yici

IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1727-1739 [Periódico revisado por pares]

New York: IEEE

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4
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach
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Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach

Pan, Jeng-Shyang ; Lee, Chiou-Yng ; Sghaier, Anissa ; Zeghid, Medien ; Xie, Jiafeng

IEEE transactions on very large scale integration (VLSI) systems, 2019-07, Vol.27 (7), p.1614-1622 [Periódico revisado por pares]

IEEE

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5
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network
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Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network

Chaurasiya, Rohit B. ; Shrestha, Rahul

IEEE transactions on very large scale integration (VLSI) systems, 2022-02, Vol.30 (2), p.166-176 [Periódico revisado por pares]

New York: IEEE

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6
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design
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Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design

Pereira, Pedro Taua Lopes ; Paim, Guilherme ; Costa, Patricia Ucker Leleu da ; Costa, Eduardo Antonio Cesar da ; de Almeida, Sergio Jose Melo ; Bampi, Sergio

IEEE transactions on very large scale integration (VLSI) systems, 2021-07, Vol.29 (7), p.1402-1415 [Periódico revisado por pares]

New York: IEEE

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7
ORION 2.0: A Power-Area Simulator for Interconnection Networks
ORION 2.0: A Power-Area Simulator for Interconnection Networks
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ORION 2.0: A Power-Area Simulator for Interconnection Networks

Kahng, A. B. ; Bin Li ; Li-Shiuan Peh ; Samadi, K.

IEEE transactions on very large scale integration (VLSI) systems, 2012-01, Vol.20 (1), p.191-196 [Periódico revisado por pares]

New York, NY: IEEE

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8
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse
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Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Kim, Jinwoo ; Murali, Gauthaman ; Park, Heechun ; Qin, Eric ; Kwon, Hyoukjun ; Chekuri, Venkata Chaitanya Krishna ; Rahman, Nael Mizanur ; Dasari, Nihar ; Singh, Arvind ; Lee, Minah ; Torun, Hakki Mert ; Roy, Kallol ; Swaminathan, Madhavan ; Mukhopadhyay, Saibal ; Krishna, Tushar ; Lim, Sung Kyu

IEEE transactions on very large scale integration (VLSI) systems, 2020-11, Vol.28 (11), p.2424-2437 [Periódico revisado por pares]

New York: IEEE

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9
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications
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Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications

Zhao, Qiang ; Peng, Chunyu ; Chen, Junning ; Lin, Zhiting ; Wu, Xiulong

IEEE transactions on very large scale integration (VLSI) systems, 2020-03, Vol.28 (3), p.848-852 [Periódico revisado por pares]

New York: IEEE

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10
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators
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FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators

Marchisio, Alberto ; Mrazek, Vojtech ; Hanif, Muhammad Abdullah ; Shafique, Muhammad

IEEE transactions on very large scale integration (VLSI) systems, 2021-04, Vol.29 (4), p.716-729 [Periódico revisado por pares]

New York: IEEE

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