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1
Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation
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Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation

Yu-Ping Liu ; Ding-Yong Hong ; Jan-Jan Wu ; Sheng-Yu Fu ; Wei-Chung Hsu

2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2017, p.343-355

IEEE

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2
LnQ: Building High Performance Dynamic Binary Translators with Existing Compiler Backends
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LnQ: Building High Performance Dynamic Binary Translators with Existing Compiler Backends

Chun-Chen Hsu ; Pangfeng Liu ; Chien-Min Wang ; Jan-Jan Wu ; Ding-Yong Hong ; Pen-Chung Yew ; Wei-Chung Hsu

2011 International Conference on Parallel Processing, 2011, p.226-234

IEEE

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An event-based language for dynamic binary translation frameworks
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An event-based language for dynamic binary translation frameworks

Makarov, Serguei ; Brown, Angela Demke ; Goel, Ashvin

2014 23rd International Conference on Parallel Architecture and Compilation Techniques (PACT), 2014, p.499-500

ACM

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Function profiling for embedded software by utilizing QEMU and analyzer tool
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Function profiling for embedded software by utilizing QEMU and analyzer tool

Tran Van Dung ; Taniguchi, Ittetsu ; Hieda, Takuji ; Tomiyama, Hiroyuki

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013, p.1251-1254

IEEE

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5
Vapor: Virtual Machine Based Parallel Program Profiling Framework
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Vapor: Virtual Machine Based Parallel Program Profiling Framework

Yusong Tan ; Wei Chen ; Qingbo Wu

2010 IEEE 16th International Conference on Parallel and Distributed Systems, 2010, p.670-675

IEEE

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6
Dynamic binary translation to a reconfigurable target for on-the-fly acceleration
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Dynamic binary translation to a reconfigurable target for on-the-fly acceleration

Kinsman, Phillip ; Nicolici, Nicola

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, p.286-287

New York, NY, USA: ACM

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7
Translating Traditional SIMD Instructions to Vector Length Agnostic Architectures
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Translating Traditional SIMD Instructions to Vector Length Agnostic Architectures

Fu, Sheng-Yu ; Hsu, Wei-Chung

2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2019, p.275-275

IEEE

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8
Dual-Engine Cross-ISA DBTO Technique Utilising MultiThreaded Support for Multicore Processor System
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Dual-Engine Cross-ISA DBTO Technique Utilising MultiThreaded Support for Multicore Processor System

Ooi, Joo-On ; Hussin, Fawnizu Azmadi B. ; Zakaria, Nordin

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC), 2016, p.257-264

IEEE

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9
Fine-Grained Overhead Analysis Utilizing Atomic Instructions for Cross-ISA Dynamic Binary Translation on Multicore Processor
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Fine-Grained Overhead Analysis Utilizing Atomic Instructions for Cross-ISA Dynamic Binary Translation on Multicore Processor

Oni, Joo-On ; Hussin, Fawnizu Azmadi ; Zakaria, Nordin

2018 International Conference on Intelligent and Advanced System (ICIAS), 2018, p.1-6

IEEE

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10
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
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Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators

Baiocchi, José A. ; Childers, Bruce R.

2009 46th ACM/IEEE Design Automation Conference, 2009, p.744-749

New York, NY, USA: ACM

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